International Business Machines Corporation

Harris C Jones

Daniel C Edelstein

James Gardner Ryan

Stefan Schmitz

Bachir Dirahoui

Christopher N Collins

James Patrick Norum

Robert C Greenlese

Michael S Barnes

John C Forster

John H Keller

James Anthony O'Neill

Chang-Ching Kin

Michael A Fury

Melanie M Chow

A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Process for making a planar integrated circuit interconnect

A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Process of manufacturing a DRAM cell capacitor having increased trench capacitance

A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the second spacers with a material to form the wiring pattern.

Technique for extending the limits of photolithography

Planar integrated circuit interconnect

DRAM cell capacitor having increased trench capacitance

A CHF.sub.3 -based RIE etching process is disclosed using a nitrogen additive to provide high selectivity of SiO.sub.2 or PSG to Al.sub.2 O.sub.3, low chamfering of a photoresist mask, and low RIE lag. The process uses a pressure in the range of about 200-1,000 mTorr, and an appropriate RF bias power, selected based on the size of the substrate being etched. The substrate mounting pedestal is preferably maintained at a temperature of about 0.degree. C. Nitrogen can be provided from a nitrogen-containing molecule, or as N.sub.2. He gas can be added to the gas mixture to enhance the RIE lag-reducing effect of the nitrogen.

Selective fluorocarbon-based RIE process utilizing a nitrogen additive

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Stormville, NY, United States of America

Harris C Jones