Spansion Llc.

Advanced Micro Devices Corporation

Globalfoundries Inc.

Advnaced Micro Devices, Inc.

Harpreet Kaur Sachar

Kuo-Tung Chang

Hidehiko Shiraiwa

Unsoon Kim

Takashi Whitney Orimoto

Youseok Suh

Angela Tai Hui

Shenqing Fang

Hiroyuki Kinoshita

Lei Xue

Amol Ramesh Joshi

Yu Nan Sun

Calvin T Gabriel

Mark W Randolph

Mark S Chang

Simon S Chan

Ning Cheng

Wei Zheng

Yider Wu

Chih-Yuh Yang

Joong Jeon

Meng Ding

Satoshi Torii

Huaqiang Wu

Jayendra D Bhakta

Hiro Kinoshita

Phillip Lawrence Jones

David H Matsumoto

Lovejeet Singh

Scott Allan Bell

Zhigang Wang

Robert B Ogle

Kashmir S Sahota

Rinji Sugino

Krishnashree Achuthan

Chih Yuh Yang

Jean Yee-Mei Yang

Allison Holbrook

Yukio Hayakawa

Hiroyuki Nansei

Christopher H Raeder

Tim Thurgate

Jack F Thomas

Christopher Foster

Boon-Yong Ang

Takayuki Maruyama

Christopher M Foster

Yu Sun

Krishnaree Achuthan

Kashmir Singh Sahota

A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.

System and method for improving reliability in a semiconductor device

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Self-aligned STI with single poly for manufacturing a flash memory device

A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

Memory cell system with charge trap

A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.

Memory system with protection layer to cover the memory gate stack and methods for forming same

A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.

Non-volatile memory device with improved erase speed

An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Integrated circuit memory system employing silicon rich layers

A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.

SONOS memory cell having high-K dielectric

A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Shallow trench isolation approach for improved STI corner rounding

A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.

Oxygen elimination for device processing

A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

Non-critical complementary masking method for poly-1 definition in flash memory device fabrication

A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with NO.

Method of forming a memory device having improved erase speed

A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.

One stack with steam oxide for charge retention

Growing community of inventors

Sunnyvale, CA, United States of America

Harpreet Kaur Sachar