International Business Machines Corporation

Harold Wayne Chase

Malcolm Scott Ware

Fariborz Assaderaghi

Norman Karl James

Stephen Larry Runyon

Soraya Ghiasi

Joshua D Friedrich

Michael Stephen Floyd

Stanislav Polonsky

David Lewis Gardell

Andrew J Geissler

Daniel Ray Knebel

Steven Paul Hartman

Jody John Van Horn

Dennis R Conti

Pia Naoko Sanda

James M Crafts

Richard L Willaman

Jagat V Pokala

Andrew T Holle

Adrian Patrascu

Dennis G Menzer

Joshua David Friedrich

Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.

Programmable active thermal control

During manufacture, an operating range for dynamic voltage and frequency scaling can be established. A nominal operating point is identified based on a design nominal operating frequency for a computer processor. The nominal operating point comprises a nominal operating voltage identified for the design nominal operating frequency. In dependence upon the nominal operating point, an operating range of frequency and voltage over which the computer processor is to function is determined. Information specifying the nominal operating point and the operating range is stored in non-volatile storage associated with the computer processor.

Establishing an operating range for dynamic frequency and voltage scaling

A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.

Identifying deterministic performance boost capability of a computer system

A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes a method such as, but not limited to, time resolved photon emission to observe transistor level switching activity in an integrated circuit (IC).

Method for VLSI system debug and timing analysis

A capacitor structure ( ) is implemented in an integrated circuit chip ( ) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body ( ) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions ( ) on both lateral sides of this device body ( ). These lateral regions ( ) are formed from a second semiconductor material. A dielectric layer ( ) is formed over both lateral regions ( ) and the device body ( ), while an anode layer ( ) is formed over the dielectric layer in an area defined by the device body. Each lateral region ( ) is coupled to ground at a first end ( ) of the elongated device body ( ). The anode ( ) is coupled to the chip supply voltage at a second end ( ) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Method for producing an integrated circuit capacitor

A capacitor structure (,) is implemented in an integrated circuit chip (,) along with other devices at the device level in the chip structure. The capacitor structure includes an elongated device body (,) formed from a first semiconductor material. This device body (,) is bordered on both lateral sides by lateral regions (,) formed from a second semiconductor material. A dielectric layer (,) overlays both lateral regions (,) and the device body (,), while an anode layer (,) overlays the dielectric layer in an area defined by the device body. Each lateral region (,) is coupled to ground at a first end (,) of the elongated device body (,). The anode (,) is coupled to the chip supply voltage at a second end (,) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Decoupling capacitor structure

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Harold Wayne Chase