Arista Networks, Inc.

Harold Wang

Prasad V Venugopal

Pranav Devalla

Aravind Musunuri

Arul Ramalingam

John Peach

Ankush Dhar

Martin Hull

A flash definition specifying a flashing sequence for a status indicator of a multi-lane port is stored on a device. In operation, the status indicator is lit, following the flashing sequence, to indicate a current lane state (in a Port/Lane Signaling Mode) or interface/channel state (in an Interface/Channel Signaling Mode). The flashing sequence may begin with a preamble, indicating a start of the flashing sequence. The device may have different multi-lane ports, each having one or more status indicators configured for indicating states of multiple lanes or a state of an interface having a multiple of component lanes. Flashing sequences for these ports are synchronizable (to the port having the largest number of lanes or, in the Interface/Channel Signaling Mode, the largest number of configured interfaces on that port). The lanes of a multi-lane port may operate at the same or different speeds and may be bundled into interfaces/channels.

System and method for signaling interface status using a single indicator

A network device having improved thermal cooling is provided. The network device includes a first printed circuit board (PCB) having a plurality of common connectors and one or more second PCBs, each second PCB coupled to the first PCB by a respective common connector of the plurality of common connectors. Each second PCB may include a set of ports, each port in the set of ports coupled to the respective common connector via the second PCB. The one or more second PCBs may be arranged vertically parallel on a front side of the first PCB such that each second PCB forms a 90 degree angle with the first PCB to allow air to flow in spaces defined between vertically adjacent second PCBs.

Linecard system using riser printed circuit boards (PCBS)

A network device having improved thermal cooling is provided. The network device comprising a first printed circuit board (PCB) having a plurality of common connectors and one or more second PCBs, each second PCB coupled to the first PCB by a respective common connector of the plurality of common connectors. Each second PCB may include a set of ports, each port in the set of ports coupled to the respective common connector via the second PCB. The one or more second PCBs may be arranged vertically parallel on a front side of the first PCB such that each second PCB forms a 90 degree angle with the first PCB to allow air to flow in spaces defined between vertically adjacent second PCBs.

Embodiments of the present disclosure provide a method and apparatus for reducing cross talk among pins in a connector. The apparatus may detect a bit error rate (BER) for each of a plurality of pins in a connector and compare the BER for each pin to a threshold BER. Responsive to determining that a set of pins among the plurality of pins each have a BER that is above the threshold BER, the apparatus may decrease the BER for each pin in the set of pins by selecting a subset of pins among the plurality of pins and adjusting operational characteristics of one or more of the subset of pins. The operational characteristics include a transmit power of the pin.

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Santa Clara, CA, United States of America

Harold Wang