Mostek Corporation

Other

Hewlett-packard Company

Foundry Networks, Inc.

Chiaro Networks Ltd

Thomson Components-mostek Corporation

Convex Computer Corporation

Jeremy Benjamin As Receiver for Chiaro Networks Ltd.

Harold Wallace Dozier

Tony M Brewer

Harry C Blackmon

Thomas C McDermott, Iii

Dean E Walker

Steven Jeffrey Wallach

Gregory S Palmer

Jim Kleiner

Keith W Shaw

David Traylor

Thomas M Jones

Arthur T Kimmel

Robert S Green

Dwight Jaynes

Chris Davies

Lou Yeh

Jeffrey H Gruger

Terrel L Morris

Gary Belgrave Gostin

David M Chastain

William D O'Leary

Vernon G McKenny

John W Clark

James R Weatherford

James E Mankovich

Alan D Gant

David A Nobles

Pat Hom

Michael C Harris

William H Wallace

Steven M Rowan

Kent A Fuka

Frank J Marshall

Gilbert J Hansen

John M Golenbieski

Gaynel J Lockhart

Gerald Matulka

Michael E Sydow

Larry W Spry

Vernon D McKenny

Harold D Shelton

Steven Craig Eplett

Robert B Kolstad

Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric. Under error-free normal conditions, however, the PFMs select a chunk arbitrarily from a default switch fabric. In this way, each chunk in real time is selected from a non-defective source and is thus guaranteed to be error free. Accordingly, if a switch fabric fails, no information chunks are lost anywhere in the system.

Router switch fabric protection using forward error correction

A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There can be a random choice of available scrambler seeds for any particular chunk to avoid malicious forcing of zero and one patterns or run lengths of bit zeroes and ones. There are a chunk cyclical redundancy check (CRC) as well as forward error correction (FEC) bytes to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format. 'Break Bytes' and 'Make Bytes' fields located at the beginning of a chunk preamble precondition an optical receiver to a proper state before the actual chunk arrives at the receiver.

System and method for router data aggregation and delivery

An integrated circuit implementation methodology uses mutable cells, e.g. cells that are capable of being personalized for use as one of a plurality of resource types. For example, a mutable cell is designed to have a component layout and a set of lower-layer internal connections compatible with both a design of a flip-flop, and a design of a pair of multiplexers. Independent customizations of the mutable cell, using higher layers of interconnect, efficiently use the cell as a flip-flop or as a pair of multiplexers. Use of mutable cells in an integrated circuit advantageously enables a set of predefined lower-layer photomask, such as for a predefined base array, to be efficiently shared among different applications. In some embodiments, a Simultaneous Dynamical Integration (SDI) Electronic Design Automation (EDA) flow advantageously uses mutable cells, such as to balance demand for resources against supply thereof.

Mutable cells for use in integrated circuits

A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There are forward error correction (FEC) bytes as well as a chunk cyclical redundancy check (CRC) to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format. 'Break Bytes' and 'Make Bytes' fields located at the beginning of a chunk preamble precondition an optical receiver to a proper state before the actual chunk arrives at the receiver.

A router line card is partitioned to separate the packet forwarding functions from physical port interfacing. For each packet forwarding card, at least one redundant port interface is provided. Identical input packets are transmitted via these redundant input port interfaces, one of which is eventually selected based on, for example, SONET standard criteria. If there is a failure, the router selects the interface path that is operating properly and rejects the path containing a failed element. Thus, the router decides locally how to correct the problem internally. Moreover, following an equipment failure the now offline failed interface path can be replaced, while the equipment remains in service using the duplicated interface path. The system can be restored to full duplex operation without affecting the existing traffic, providing for a hot replacement of a failed path. Because the interfaces are separate, a failed module can be renewed and replaced while the equipment is in service. If a failure occurs in an interface card between two peer routers, then packets flow between the two routers uninterrupted from exactly the same previous ports on one router to the same previous ports on the second router, using the same Internet protocol addresses as existed prior to the switching.

Router network protection using multiple facility interfaces

Router line cards are partitioned, separating packet forwarding from external or internal interfaces and enabling multiple line cards to access any set of external or internal data paths. Any failed working line card can be switchably replaced by another line card. In particular, a serial bus structure on the interface side interconnects any interface port within a protection group with a protect line card for that group. Incremental capacity allows the protect line card to perform packet forward functions. Logical mapping of line card addressing and identification provides locally managed protection switching of a line card that is transparent to other router line cards and to all peer routers. One-for-N protection ratios, where N is some integer greater than two, can be achieved economically, yet provide sufficient capacity with acceptable protection switch time under 100 milliseconds. Alternatively, protect line cards can routinely carry low priority traffic that is interruptible, allowing the protect line card to handle higher priority traffic previously carried by a failed working line card. This approach renders unnecessary engineering a network for less than full capacity to allow rerouting in the event of individual line card failure. Consequently, all data paths can be fully utilized. If a particular interface module on one data bus needs removal for maintenance, a duplicate data bus is available intact, allowing hot replacement of any working or protect interface module, even while a line card protection switch is in effect.

Router line card protection using one-for-N redundancy

Information and control are synchronized as they flow through a large distributed IP router system with independent clocks. The IP router includes multiple equipment racks and shelves, each containing multiple modules. The IP router is based on a passive switching device, which in some embodiments is an optical switch. Control and data come to the switching device from different sources, which have different clocks. Timing and synchronization control are provided, such that information and control both arrive at the switching device at the proper time. A single point in the system originates timing, which is then distributed through various ASICs of the system to deliver configuration control to the switch at the appropriate time. The launch of information to the switch is also controlled with a dynamic feedback loop from an optical switch controller. Control aspects of the optical switch are aligned by this same mechanism to deliver control and data to the optical switch simultaneously.

Timing and synchronization for an IP router using an optical switch

A system for testing an integrated circuit. The system includes a plurality of simultaneous switching output (SSO) cells with each of the plurality of simultaneous SSO cells including an output driver providing an output signal to a respective signal pin coupled to the integrated circuit, a toggle circuit toggling its output; a multiplexer selecting a signal for communication to the output driver to control output provided to the respective signal pin, an input signal line communicating an SSO enable signal to the multiplexer, wherein the multiplexer selects the toggled output for communication to the output driver when the SSO enable signal is asserted; and a signal pin that is coupled to each respective input signal line of the plurality of SSO cells.

Multipurpose test chip input/output circuit

A method and apparatus for reducing noise in integrated circuit chips (ICs). The apparatus comprises on-die capacitance in conjunction with one or more resistive loss elements, which provide an AC termination for on-die power events. The on-die capacitance can be instantiated in metal layers alone, in gate oxides or in gate oxides combined with metal structures. The capacitance may be provided by the capacitive characteristics of adjacent metal layers of the power distribution structure of the IC. When the capacitance is provided in this manner, the resistive loss element corresponds to the linear resistance of thin lines on the metal layers of the power distribution structure. The resistive loss element may, alternatively, be comprised of a field effect transistor (FET) or a metal oxide semiconductor field effect transistor (MOSFET). By utilizing on-die capacitance in conjunction with one or more resistive loss elements, the IC is provided with loss characteristics and power filter characteristics that are effective in reducing power noise and EMI. The method ensures that the values of the resistive loss element and of the capacitance element are selected for optimum reduction of power noise without causing on-die resonance.

Method and apparatus for reducing noise in integrated circuit chips

The inventive system and method determines path delay of at least one test path of logic gates. The invention uses a toggle register to generate a toggling signal, that is sent out onto the path by a launch register. A capture register receives the signal from the other end of the path. A logic gate compares the received signal from a prior launched signal with an inverted launched signal. Since the signal is a toggling signal the prior received signal should be the same as an inverted launched signal. A latch register determines whether the logic gate has detected a match between inverted launched signal and the received signal from a prior launch signal within a predetermined time clock period. As the clock period is shortened, the launched signal will fail to traverse the path and be captured by the capture register within the clock period. This will cause a mis-match in the logic gate. The clock period at the point of mis-match is the delay time of the path. The invention can use two paths to produce a very accurate comparison of the delays on the two paths.

Test chip circuit for on-chip timing characterization

An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80). The operand processing unit (10) provides concurrent processing of operands to enhance processing speed. The operands and resultants are handled in a manner such that there is a uniform and sequential flow of operands from a source, such as main memory, and a uniform and sequential delivery of resultants to a destination, such as a memory or input/output device.

Concurrent processing of data operands

An auxiliary connector circuit is used within an electronic system (10) which comprises a plurality of removable circuit cards (14, 16, 18, 20, 22, 24, 26) which are mounted within a cabinet (12). Before the circuit card (16) is removed from the cabinet (12), a power cable (44) is connected by means of engaging a plug (46) to a socket (34). When this occurs a DATA OUT ENABLE signal at a line (65) drives three-state devices (86, 88, 90, 92, 94, 96, 98 and 100) to a high impedance state to isolate a memory array (78) from a data bus (102). This high impedance prevents any transients from being transmitted through the data bus (102) when the card (16) is removed from the cabinet (12). After the card (16) is removed from the cabinet (12), the power cable (44) can be disconnected from the card (16) or the card (16) can be tested to evaluate the components mounted on the card (16).

Auxiliary power connector and communication channel control circuit

A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer there is included the logical data cache which stores data at logical addresses such that the central processor can store and retrieve data without the necessity of first making a translation from logical to physical address.

Computer system

A microcomputer has provision for both on-chip ROM (on the same chip as the CPU) and off-chip ROM and which may operate with only on-chip ROM as only off-chip ROM has the hardware capability to disable on-chip ROM permanently, so that chips having defective ROM may be salvaged by being converted to computer chips that use only off-chip ROM.

Microcomputer with severable ROM

Growing community of inventors

Dallas, TX, United States of America

Harold Wallace Dozier