International Business Machines Corporation

Qualcomm Incorporated

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Cray Incorporated

Harold Wade Cain, Iii

Michael K Gschwind

Maged M Michael

Valentina Salapura

Fadi Y Busaba

Eric M Schwarz

Chung-Lung K Shum

Timothy John Slegel

David Michael Daly

Dan F Greiner

Vijayalakshmi Srinivasan

Mauricio J Serrano

Jose Eduardo Moreira

Kattamuri Ekanadham

Hung Qui Le

Jong-Deok Choi

Jason Zebchuk

Brian Robert Prasky

Bradly George Frey

Cathy May

Shivam Priyadarshi

Gheorghe Calin Cascaval

Derek Robert Hower

Michael Huang

Hubertus Franke

Pratap Chandra Pattnaik

Colin B Blundell

Christian Jacobi

Derek E Williams

Jonathan D Bradbury

Charles Ray Johns

Carl Alan Waldspurger

Ravi Nair

Hong Min

Bryan J Lloyd

Donna N Dillenberger

Richard Loise Arndt

Michel H T Hack

Gong Su

James Zu-Chia Teng

Shih-Hsiung Stephen Tung

Xiaotong Zhuang

Sanyam Mehta

Rami Mohammad A Al Sheikh

Daniel Jonathan Ernst

Nagesh Bangalore Lakshminarayana

Brandon Harley Anthony Dwiel

James Allan Kahle

Naresh Nayar

Randal Craig Swanberg

Thomas Philip Speier

Ryan Donovan Wells

Jeffrey Todd Bridges

Eric Francis Robinson

Brian Stempel

Garrett M Drapala

Rabin Sugumar

Xiaowei Shen

Takuya Nakaike

Robert J Blainey

Rami Mohammad Al Sheikh

David Scott Ray

Ali Ijaz Sheikh

Joseph Gerald McDonald

Roberto Avanzi

Vignyan Reddy Kothinti Naresh

Rosario Cammarota

Benjamin Herrenschmidt

Rui Hou

Timothy J Siegel

Toshihiko Koju

Huayong Wang

Sanjay Bhikhubhai Patel

Gabriel Martel Tarr

Darren Lasko

Priya Ashok Nagpurkar

Niket Choudhary

Nikhil Narendradev Sharma

SeyedMajid Zahedi

Chih Kang Lin

Ramesh Chandra Chauhan

Utkarsh Mathur

A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Memory access request for a memory protocol

A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

Method and apparatus for back end gather/scatter memory coalescing

Method and apparatus for front end gather/scatter memory coalescing

An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

Method, apparatus, and system for memory bandwidth aware data prefetching

Managing prefetch requests associated with memory access requests includes storing stream information associated with multiple streams. At least one stream was recognized based on an initial subset of memory access requests within a previously performed set of related memory access requests and is associated with stream information that includes stream matching information and stream length information. After the previously performed set has ended, a matching memory access request is identified that matches with a corresponding matched stream based at least in part on stream matching information within stream information associated with the matched stream. In response to identifying the matching memory access request, the managing determines whether or not to perform a prefetch request for data at an address related to a data address in the matching memory access request based at least in part on stream length information within the stream information associated with the matched stream.

Managing prefetch requests based on stream information for previously recognized streams

A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

Dynamic update of the number of architected registers assigned to software threads using spill counts

Systems and methods are directed to managing access to a shared memory. A request received at a memory controller, for access to the shared memory from a client of one or more clients configured to access the shared memory, is placed in at least one queue in the memory controller. A series of one or more timeout values is assigned to the request, based, at least in part on a priority associated with the client which generated the request. The priority may be fixed or based on a Quality-of-Service (QoS) class of the client. A timer is incremented while the request remains in the first queue. As the timer traverses each one of the one or more timeout values in the series, a criticality level of the request is incremented. A request with a higher criticality level may be prioritized for servicing over a request with a lower criticality level.

QoS-class based servicing of requests for a shared resource

A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

Indicator-based prioritization of transactions

A scheme referred to as a 'Region-based cache restoration prefetcher' (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the 'cold' cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.

Methods of cache preloading on a partition or a context switch

Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein.

Database system transaction management

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements

A computer-implemented method for cache memory management includes receiving a coherence request message from a requesting processor. The method can further include determining a request type responsive to detecting the transactional conflict. The request type is indicative of whether the coherence request is a prefetch request. The method further includes detecting, with a conflict detecting engine, a transactional conflict with the coherence request message. The method further includes sending, with the adaptive prefetch throttling engine, a negative acknowledgement to the requesting processor responsive to a determination that the coherence request is a prefetch request.

Cache memory transaction shielding via prefetch suppression

A transactional memory system determines whether a hardware transaction can be salvaged. A processor of the transactional memory system begins execution of a transaction in a transactional memory environment. Based on detection that an amount of available resource for transactional execution is below a predetermined threshold level, the processor determines whether the transaction can be salvaged. Based on determining that the transaction can not be salvaged, the processor aborts the transaction. Based on determining the transaction can be salvaged, the processor performs a salvage operation, wherein the salvage operation comprises one or more of: determining that the transaction can be brought to a stable state without exceeding the amount of available resource for transactional execution, and bringing the transaction to a stable state; and determining that a resource can be made available, and making the resource available.

Determining if transactions that are about to run out of resources can be salvaged or need to be aborted

When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

Hint instruction for managing transactional aborts in transactional memory computing environments

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Raleigh, NC, United States of America

Harold Wade Cain, Iii