Agere Systems Inc.

Telephonics Corporation

Harold Simmonds

Dale Harvey Nelson

Johannes Gerardus Ransijn

Wenzhe Luo

Zhigang Ma

James D Yoder

Lizhong Sun

King-Hon Lau

William Eric Holland

Xiangqun Sun

A bidirectional integrated CMOS switch is provided which is capable of switching voltages beyond the range of the supply and ground potentials. The switch is composed of NMOS and PMOS transistors as the switch conductor path, a diode bridge, and control circuitry to turn the switch on and off by means of low voltage logic, regardless of the voltages on the switch terminals. The device and method of the invention enables the switching of high voltage loads operating at arbitrary or floating voltages relative to the low voltage power supply and ground, and provides on/off control of the switch with ordinary low voltage logic levels. The invention provides bidirectional switching without conducting through the parasitic body diodes of the CMOS devices.

Bidirectional integrated CMOS switch

The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the &#x3a3;&#x394; rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Serial protocol for agile sample rate switching

In accordance with described exemplary embodiments, correction is inserted into the feedback loop of a second order resonator used at the time of frequency transition. The correction is based upon parameters generated from a desired output signal frequency and a desired sampling frequency. The correction is generated to maintain i) constant amplitude, ii) continuous phase, and iii) the same sampling frequency during the frequency transition.

Digital sine wave generator

A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Fractional-N baseband frequency synthesizer in bluetooth applications

Growing community of inventors

Stewartsville, NJ, United States of America

Harold Simmonds