International Business Machines Corporation

Nec Research Institute, Inc.

Nec Laboratories America, Inc.

Other

Harold S Stone

Kadathur S Natarajan

Philip Heidelberger

Chung-Sheng Li

Matthew Lynn Miller

Joel Leonard Wolf

Mark B Ritter

Thomas R Puzak

Ingemar J Cox

Ismail C Noyan

Mark B Reinhold

Mark F Bregman

Karen Liu

Franklin F Tong

Michael Orchard

Amar Mukherjee

Thomas Wren Ebbesen

William C Brantley, Jr

Talal G Shamoon

Robert Wolpov

Majd F Sakr

Janice Murphy Stone

EE-Chien Chang

Stephen Martucci

A method for registration of first and second images out of registration. The method includes the steps of: (a) making the edges in the first and second images more prominent; (b) thresholding the first and second images from the previous step using a threshold for which N percent of the pixels of each of the first and second images are over the threshold; (c) reducing the resolution of the first and second images from the previous step; and (d) registering the first and second images of reduced resolution from the previous step.

Method for blind cross-spectral image registration

Methods for registering first and second images which are offset by an x and/or y displacement in sub-pixel locations are provided. A preferred implementation of the methods includes the steps of: multiplying the first image by a window function to create a first windowed image; transforming the first windowed image with a Fourier transform to create a first image Fourier transform; multiplying the second image by the window function to create a second windowed image; transforming the second windowed image with a Fourier transform to create a second image Fourier transform; computing a collection of coordinate pairs from the first and second image Fourier transforms such that at each coordinate pair the values of the first and second image Fourier transforms are likely to have very little aliasing noise; computing an estimate of a linear Fourier phase relation between the-first and second image Fourier transforms using the Fourier phases of the first and second image Fourier transforms at the coordinate pairs in a minimum-least squares sense; and computing the displacements in the x and/or y directions from the linear Fourier phase relationship. Also provided are a computer program having computer readable program code and program storage device having a program of instructions for executing and performing the methods of the present invention, respectively.

Method for subpixel registration of images

A transmitter for transmitting data in the form of an optical signal. The transmitter having: a transmitter chip module having a material capable of radiating light of a first wavelength when both a zero voltage potential exists across the material and when illuminated by light of a second wavelength; a light source optically coupled to the transmitter chip module for illuminating the material with light of the second wavelength; and a voltage controller for controlling the voltage potential across the first material. Also provided is a receiver for receiving data in the form of an optical signal having a first wavelength. The receiver having: a receiver chip module having a material capable of producing a signal in the form of a produced voltage potential or produced current when illuminated by light of both the first wavelength and light of a second wavelength; a light source optically coupled to the receiver chip module for illuminating the material with light of the second wavelength; and a signal detector for detecting presence of the produced signal.

Apparatus and method for transmitting data between VLSI chips

A method for prefetching structured data, and more particularly a mechanism for observing address references made by a processor, and learning from those references the patterns of accesses made to structured data. Structured data means aggregates of related data such as arrays, records, and data containing links and pointers. When subsequent accesses are made to data structured in the same way, the mechanism generates in advance the sequence of addresses that will be needed for the new accesses. This sequence is utilized by the memory to obtain the data somewhat earlier than the instructions would normally request it, and thereby eliminate idle time due to memory latency while awaiting the arrival of the data.

Method for perfetching structured data

This invention enables progressively higher resolution images of a JPEG compressed image to be produced in a cost effective manner during the JPEG decompression process. The operation count is very low when images of {fraction (1/64)}th, {fraction (1/16)}th, and &frac14;th of full resolution are to be produced without doing a full JPEG decompression. The low resolution images are useful for high speed search, and the ability to produce them without doing full decompression is an important factor in making such search practical.

Progressive JPEG decoding

A multiresolution method and apparatus for searching of a database of images where the search is performed on compressed images, without first decompressing them. The method searches the database of compressed images first at a low resolution to obtain the relative quality of a match between a search template and a candidate image. If the match is below a particular threshold, the search is terminated without committing any further computational resources to the search. Conversely, if the match is above a particular threshold, the method enhances the resolution of the candidate image and then performs another match. As long as the relative quality of the match is above the particular threshold, the resolution of the candidate image is successively enhanced, until a match determination is made at a full resolution of the candidate image.

Method and apparatus for multi-resolution image searching

A method for finding a match between a pattern of data of relatively small size in a base of related data or relatively large size in the presence of occlusions which are gaps or noise that obscure portions, either of the pattern or of the base. The method involves masking out occluded points in both the base data and the pattern so that correlation can be computed only at those points that are not occluded.

Method for computing correlation operations on partially occluded data

A operand prefetching mechanism is described for a system having a cache, in addition to its normal memory. The prefetch apparatus utilizes a table that records the location of each instruction that caused an operand miss and the location of the miss. Associated with this information is the address of each instruction fetch block that contains an instruction that caused an operand miss. The table is called an Operand Prefetch Table. With each instruction block fetched from the cache a search is made of the Operand Prefetch table to determine if the instructions found in this block previously caused operand misses. If the instruction block fetched matches an entry in the Operand Prefetch Table then a prefetch for future operands can be attempted for the instructions contained within the instruction block fetch segment.

Operand prefetch table

Using this invention, more than one variable that is shared in a multiprocessing environment can be updated atomically. Each computer processor operating in the multiprocessing environment contains more than one reservation register which, along with this novel method, are used to place reservations on each of more than one shared variable. During the execution of a program, a plurality of shared variables can be reserved, each by its respective reservation register. A reservation is placed on a shared variable by means of a special instruction. The reservation register keeps track of: the address of the shared variable that it is reserving, the value of the modified results that are to be updated in the shared variable address, whether the variable has been updated, whether the reservation is valid, and whether the processor containing the reservation register has a privilege to update the shared variable. A reservation can be invalidated if a second processor tries to read the address of the reserved shared variable. When an instruction is encountered that tries to update a shared variable, the set of reserved modified shared variables designated by that instruction that have unupdated modified results are updated atomically if and only if all the reservations in the designated set are valid. If any of the reservations in the set are invalid, no shared variable in the set is updated. A condition code reports if the update was successful or did not occur. The condition code can be tested so that the sequence of instructions can be repeated until it is successful.

Posting multiple reservations with a conditional store atomic operations

A computer-implemented process for determining a ranked set of solutions to a bipartite graph matching problem, such is involved in multi-target tracking, maximum flow matching, or data association in matching elements of a first set to elements of a second set to minimize the cost of the association. A feature of the process is a partitioning into subproblems such that the most probable solutions are in the smaller subproblems and the computation begins by solving the smallest subproblem in the search for the best solution.

Method for determining a ranked set of associations

A Write/Load cache protocol is described which may be used for maintaining cache coherency and performing barrier synchronization in multiprocessor computer systems, and for cooperating with prefetch mechanisms to allow data to be loaded into a central processor unit's (CPU) cache (in both single and multiprocessor systems) in anticipation of future memory references. The new protocol is defined such that when a cache observes a Write/Load command (and associated data item) on a bus to which the cache is attached, the cache is accessed and (a) if the data item is in the cache, the new value of the data item from the bus is copied into and replaces the data item in cache; and (b) if the data item is not in the cache, a new data item is created therein (preferably using the normal cache replacement policy), and the value of the data item on the bus is loaded into the cache. Thus, a protocol is provided which allows cache to be loaded via an external entity, i.e., other than the processor being directly serviced by the cache.

Methods and apparatus for performing a write/load cache protocol

The invention is a system and method for improving the signal-to-noise ratio of an electrical data signal transmitted between two electronic modules. An electrical data signal from a first module is amplified by an electrical amplifier to produce an amplified electrical data signal. The electrical amplifier is supplied by a power distribution network. The amplified electrical data signal has a power level sufficiently low such that the electrical amplifier does not cause significant disturbances in the power distribution network so that a plurality of the electrical amplifiers can be proximately located and operated concurrently without significant noise coupling occurring between the electrical amplifiers through the power distribution network. The electrical data signal is then converted to an optical data signal for transmission to a second module. The optical data signal is transmitted to the second module through an optical path where it is optically amplified. The amplified optical data signal is then received at the second module and detected to produce an electrical signal which has a substantially improved signal-to-noise ratio.

Interconnections having improved signal-to-noise ratio

A combining switch that reduces memory accesses, synchronizes parallel processors and is easy to implement, is achieved by configuring a plurality of parallel processing nodes in a ring arrangement and by implementing a synchronizing instruction for the switch that facilitates, rather than inhibits, parallel processing. According to the preferred embodiment of the invention the ring is a token ring and the synchronizing instruction is a Fetch-and-Add instruction.

Combining switch for reducing accesses to memory and for synchronizing

A mechanism within a disk controller that computes the number of units of storage space accessed as a function of either real or virtual time. A counter is set to a reference count. Each unit of storage space has a predetermined bit set to a predetermined state indicative that the unit of storage space has not been accessed. The unit of storage space is accessed, and if the predetermined bit is in the predetermined state, the state is changed to indicate access. The counter is incremented in response to the change of state of the predetermined bit, with the count being indicative of the number of units of storage space accessed. This so-called 'footprint' function can be used by the disk controller as input for an algorithm that attempts to optimize cache performance.

Method and apparatus for calculating disk-access footprints for use in

An optical bus for interconnecting electronic devices. The bus has a substrate with through-holes therein. An optically conductive material is disposed on one side of the substrate. The material fills the through-holes and forms a layer of predetermined thickness on this side of the substrate. In the outer surface of this layer there are facets or angled regions. The surface and facets are optically reflective. Cards or modules are optically connected by means of optical connectors to the through-holes on the opposite side of the substrate. Light emitted by the connector travels to the associated faceted surface from which it reflects towards other faceted surfaces from which it is partially transmitted and partially reflected to another connector. The arrangement permits optical communication between a plurality of electronic devices.

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Princeton, NJ, United States of America

Harold S Stone