Freescale Semiconductor,inc.

Motorola Corporation

Harold M Martin

Thang Q Nguyen

Jose Melanio Nunez

Carlos A Greaves

Mark H Nodine

Gus P Ikonomopoulos

Anhtu Nguyen

Hashing and pattern matching are used in an information processing system to process incoming messages from a network such as an Ethernet-based network. Using hashing and pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. A hash function and a pattern matching function are performed on a message received by an information processing system, and the message is selectively accepted based on at least one of a hash result and a pattern matching result. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches.

Network message filtering using hashing and pattern matching

A maximum timeout time for a communication between devices is determined. A time period is determined for a plurality of time zones based upon the maximum timeout time. A current time zone is updated every time period. A timeout zone for an outstanding transaction is associated with a first time zone to indicate when the outstanding transaction will timeout if not completed. In one embodiment, the time period for each time zone is approximately equal to the maximum timeout period divided by a predetermined number of time zones, which may be the total number of time zones, e.g. eight or sixteen.

Method of monitoring timeout conditions and device therefor

Network message processing using inverse pattern matching

A method and technique for verifying bus protocol in the design of integrated circuits. A correctness evaluator receives simulation results from a monitor file and prediction information generated from protocol templates. The correctness evaluator operates according to a 'clean bus' theory that an error includes those events not specified by the circuit specification, including spurious transitions. Protocol templates define the elements within the circuit, and are provided to a prediction generator which creates a prediction file. The correctness evaluator compares a simulation monitor file to the prediction file, and outputs a pass or fail result. The present invention offers a flexible method to separate protocol-defined timing constraints from implementation-dependent timing constraints. The present invention allows input from a test program to tailor bus signal change predictions and verify that the test program performs as it is programmed to perform.

Method for verifying protocol conformance of an electrical interface

Growing community of inventors

Austin, TX, United States of America

Harold M Martin