USA As Represented by Secretary of the Navy

United States of America As Represented by the Secretary of the Air Force

Harold L Hughes

Patrick J McMarr

Reed K Lawrence

Francis J Kub

Robert R Whitlock

David J Godbey

Akos G Revesz

Roderick A B Devine

Bernard J Mrstik

Robert A August

Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.

Technique to radiation-harden trench refill oxides

In microelectronic circuits involving dielectric/semiconductor interfaces having interstitial sites in the dielectric, a method for hardening these interfaces by introducing a small atomic diameter inert gas into the interstitial sites.

Method for reducing device and circuit sensitivity to electrical stress and radiation induced aging

A neutron detection device includes a neutron conversion layer in close proximity to an active semiconductor layer. The device is preferably based on the modification of existing conventional semiconductor memory devices. The device employs a conventional SRAM memory device that includes an SOI substrate. The SOI substrate includes an active semiconductor device layer, a base substrate and an insulating layer between the active semiconductor device layer and the base substrate. The base substrate layer is removed from the memory device by lapping, grinding and/or etching to expose the insulating layer. A neutron conversion layer is then formed on the insulating layer. The close proximity of the neutron conversion layer to the active semiconductor device layer yields substantial improvements in device sensitivity.

Neutron detection device and method of manufacture

This invention concerns a non-volatile memory device with a polarizable layer. The apparatus concerns a substrate, a buried oxide layer within the substrate, and a polarizable layer within the substrate. The polarizable layer is formed in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. The process of creating the polarizable layer comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5&#x2013;50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25&#x2013;300 degrees Celsius. An annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Non-volatile memory device with a polarizable layer

A semiconductor substrate incorporating a neutron conversion layer (such as boron-10) that is sensitive enough to permit the counting of single neutron events. The substrate includes an active semiconductor device layer, a base substrate, an insulating layer provided between the active semiconductor device layer and the base substrate, and a neutron conversion layer provided between the active semiconductor device layer and the base substrate. The neutron conversion layer is located within the insulating layer, between the insulating layer and the base substrate or between the active semiconductive device layer and the insulating layer. A barrier layer is provided between at least one of the neutron conversion layer and the active semiconductor device layer and the neutron conversion layer and the base substrate to prevent diffusion of the neutron conversion material provided in the neutron conversion layer. Further, a plurality of trenches may be formed in the active semiconductor device layer. In such a case, a trench neutron conversion layer is formed in at least one of the trenches to improve device sensitivity.

Semiconductor substrate incorporating a neutron conversion layer

This invention concerns a process of forming a polarizable layer in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. This process comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5-50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25-300 degrees Celsius. After implantation, an annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Creation of a polarizable layer in the buried oxide of silicon-on-insulator substrates for the fabrication of non-volatile memory

The radiation hardness of a microelectronic device is improved by implant dopant ions, such as Si, into an oxide layer. This implantation creates electron traps/recombination centers in the oxide layer. A subsequent anneal remove defects in the active silicon layer.

Radiation-hardening of microelectronic devices by ion implantation into

The radiation hardness of a silicon-on-insulator structure is improved by planting dopant ions, such as Si, into the buried oxide layer. The dopant ions are implanted in the buried oxide layer, near, but not at, the active Si layer/buried oxide layer interface. This implantation creates electron traps/recombination centers in the buried oxide layer.

Radiation-hardening of SOI by ion implantation into the buried oxide

A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy includes properly doping a prime silicon wafer for the desired application, growing a strained Si.sub.1-x Fe.sub.x alloy layer onto seed wafer to serve as an etch stop, growing a silicon layer on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer and a test wafer, bonding the oxide surfaces of the test and prime wafers, machining the backside of the prime wafer and selectively etching the same to remove the silicon, removing the strained alloy layer by a non-selective etch, thereby leaving the device region silicon layer. In an alternate embodiment, the process includes implanting germanium, tin or lead ions to form the strained etch stop layer.

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West River, MD, United States of America

Harold L Hughes