General Electric Company

Harold G Parks

George E Possin

William W Piper

Donald E Castleberry

William C Hughes

Jack D Kingsley

Conilee G Kirkpatrick

James F Norton

A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.

Dual dielectric field effect transistors for protected gate structures

A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electricial and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.

A thin film FET switching element, particularly useful in liquid crystal displays (LCDs) employs particular materials and is fabricated via a particular process to ensure chemical compatibility and the formation of good electrical contact to an amorphous silicon layer while also producing FETs with desirable electrical properties for LCDs. These materials include the use of titanium as a gate electrode material and the use of N.sup.+ amorphous silicon as a material to enhance electrical contact between molybdenum source and drain pads and an underlying layer of amorphous silicon. The process of the present invention provides enhanced fabrication yield and device performance.

N.sup.+ amorphous silicon thin film transistors for matrix addressed

A thin film FET switching element, particularly useful in liquid crystal displays, employs a set of special materials to ensure compatibility with the indium tin oxide of a pixel electrode layer used as transparent conductive material in liquid crystal display devices. These materials include the use of titanium as a gate electrode material and the use of aluminum as a material to enhance electrical contact between source and drain pads and an underlying layer of amorphous silicon. The apparatus and process of the present invention provide enhanced fabrication yield and device reliability.

Process and structure for thin film transistor with aluminum contacts

Thin film transistor with aluminum contacts and nonaluminum metallization

A process for the fabrication of thin film field effect transistors in active matrix liquid crystal display devices includes the utilization of a protective, conductive tab disposed on a corner portion of the pixel electrodes. Electrical contact is made to the pixel electrodes not directly, but rather through a via opening in protective, insulative and amorphous silicon layers. The structure is particularly advantageous in that it permits the utilization of a wider range of gate and upper level metallization materials, particularly aluminum, whose etchants are otherwise found deleterious to pixel electrode material such as indium tin oxide. The structure of the present invention is seen to be readily fabricatable in accordance with high yield fabrication procedures.

Protective tab structure for use in the fabrication of matrix addressed

An organic or inorganic base solution is employed as a means for passivating the back channel region of an amorphous silicon FET device following plasma etching of the back channel region. The passivation provided significantly reduces back channel leakage currents resulting in FET devices which are compatible with conventional processing methods and which exhibit desirable properties for use in liquid crystal display systems.

Method for passivating the back channel of amorphous silicon field

The gate electrode in an inverted field effect transistor (FET) is fabricated with titanium to provide an FET which is particularly suitable for use as the switching element in a matrix addressed liquid crystal display. More particularly, the resist employed in gate electrode patterning is plasma ashed in an oxygen atmosphere to toughen the titanium gate material and render it more amenable to subsequent processing steps.

Deposition and hardening of titanium gate electrode material for use in

An improved magnetic fine deflection system, for use in an electron beam optical system of the type having a single plate matrix lens, utilizes an orthogonal set of stacked deflection-field-generating conductors, with one stacked orthogonal pair of sheet conductors being positioned behind a target, upon which the electron beam is to be focused and deflected, and with a second orthogonal pair of sheet conductors positioned in front of the multi-apertured single plate matrix lens and having apertures in registration with the lenslets. The improved magnetic fine deflection system is utilized in an electron beam optical system having first means for forming a narrow beam of electrons and coarse deflection means associated with the first means for scanning the electron beam to each lenslet of the single plate matrix lens, for passage therethrough and into the magnetic fine deflection field.

Magnetic fine deflection system comprising sheet conductors

Electron optics apparatus, for use in electron-beam lithography, electron-beam-addressable memory tubes and the like, utilizes a tri-potential collimating condenser lens and a multi-element matrix lens of the 'flys eye' type with coarse deflection elements positioned therebetween to deflect the collimated electron beam from the condenser lens to the appropriate aperture in the matrix of lenslets. The condenser lens electrode and matrix lens electrode closest to one another, as well as the coarse deflection electrodes therebetween, are substantially the only elements in the apparatus which float at a relatively high electrical potential, thereby simplifying the requirements of peripheral circuitry while retaining the advantages of the 'flys eye' matrix lens.

Electron optics apparatus

One of a multiplicity of data values is permanently recorded at each data site in a two-dimensional data site array defined upon the surface of a semiconductor diode target by implanting an auxiliary bit thereat having an associated one of a multiplicity of possible dopant concentrations, at a uniform implantation depth, or of different implantation depths, at a uniform doping concentration, into a fabricated layer of the diode, responsive to respectively controlling the fluence or the landing energy of a writing ion beam.

Methods of gray scale recording and archival memory target produced

Binary information is stored in a semiconductor archival memory medium by formation of a region of an alloy, of the semiconductor material and a non-doping material, at each of a plurality of potential memory sites at which a first binary value of information is to be stored, with the remaining data sites being devoid of the alloyed region to store the remaining value of binary data. Methods for writing the formation of the alloyed region, and reading the information value stored at each memory site, are also disclosed.

Archival memory media and method for information recording thereon

An improved fine deflection, for use in an electron beam optical system, utilizes a magnetic deflector positioned adjacent to the surface of the target most remote from a matrix lens, which is positioned between the target and an electron beam emitter. The matrix lens is a single plate having multiple apertures forming matrix lenslets and has an electron beam accelerator positioned between the lens and the target for uniform acceleration of the electron beam passing through a selected one of the lenslets.

Magnetic deflection apparatus positioned behind target

A high resolution matrix lens electron optical system utilizes a relatively short focal length matrix lens, means for providing an axial magnetic field and electrostatic deflection means for both coarse and fine deflection operation in conjunction with the axial magnetic field to provide reduced cathode loading and minimal spherical aberration.

High resolution matrix lens electron optical system

A memory plane for an archival, non-volatile mass storage memory has a planar semiconductor diode with each of a plurality of small P-N junction diodes alloyed into the surface of its fabricated layer responsive to a selectively-actuated scanned energy beam at each location corresponding to a first binary value in a planar array of data sites. Formation of a P-N junction is prevented at each of the remaining sites of the planar data array to provide storage of data having the remaining binary value. Several alternative methods for formation of the alloy junction surface diodes are disclosed.

Growing community of inventors

Scotia, NY, United States of America

Harold G Parks