International Business Machines Corporation

Harold E Reindel

David James Hathaway

Ulrich Alfons Finkler

David E Lackey

Alvar Antonio Dean

Ronald Dennis Rose

David J Widiger

Larry Wissel

Lewis William Dewey, Iii

Roger Paul Gregor

Steven N Hirsch

Paul H Bergeron

Keith M Carrig

A system and method to perform capacitance extraction involves defining a location of signal wires and floating metal of an integrated circuit design. The method includes designating one of the signal wires as a target wire, defining a first area within which first capacitances between the target wire and the floating metal and other signal wires are determined, defining a second area, within which second capacitances between floating metal within the first area and the floating metal and the other signal wires not within the first area are determined, and generating an intermediate capacitive network. The intermediate capacitive network includes the target wire, the floating metal, and the other signal wires within the second area, the first capacitances and the second capacitances. A capacitive network is generated from the intermediate capacitive network. The first capacitances and the second capacitances are used to generate third capacitance values of the capacitive network.

Capacitance extraction for floating metal in integrated circuit

A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task.

Common memory programming

A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.

Latch clustering for power optimization

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Williston, VT, United States of America

Harold E Reindel