Vlsi Technology, Inc.

Acoustic Technologies, Inc.

Harold Downey

Scott E Harrow

Judy Mae Fong

Timothy Shayne Carlson

The amplitudes of a signal on the microphone input of a telephone and a signal on the line input of the telephone are compared with each other and with two thresholds. The comparisons are sampled and the samples control an up-down counter. The count in the counter is compared with two thresholds and the results of the comparisons are used to control at least two accumulators. A first accumulator counts consecutive comparisons having the same result and a second accumulator counts up or down in accordance with the comparisons. The counts in the first and second accumulators are logically analyzed to determine whether to receive or transmit. A plurality of samples defines a window, at the end of which the up-down counter is reset. The accumulators store data from a plurality of windows.

Transmit/receive arbitrator

A method for transferring data is performed by a first input/output device in order to perform a data transaction with a host device. The first input/output device receives a first data transaction request from the host device. The first input/output device stops the first data transaction. The first input/output device then requests a data second transaction with a second input/output device and asserts a request signal. The first input output device continuously asserts the request signal even when receiving a stop signal from the second input/output device. The first input/output device retries the second data transaction with the second input/output while continuously asserting the request signal. Upon completing the second data transaction with the second input/output device, the first input/output device releases the request signal. The first input/output device then completes the data transfer with the host device.

Method for maintaining bus ownership while bus mastering

A system for transforming computer system interrupts from state based interrupts to event based interrupts. The system of the present invention includes an interrupt acknowledge detection circuit adapted to detect an interrupt acknowledge from a computer system. The interrupt acknowledge detect circuit is coupled to a vector match circuit. The vector match circuit is adapted to receive an interrupt vector from the computer system and determine whether the interrupt vector matches a predetermined interrupt vector within the vector match circuit. The vector match circuit is, in turn, coupled to an interrupt assertion circuit. The interrupt assertion circuit includes an internal interrupt request line and an external interrupt request line. The interrupt assertion circuit functions by asserting an interrupt signal via the external interrupt request line to the computer system in response to receiving a state based interrupt via the internal interrupt request line. Subsequently, the interrupt assertion circuit deasserts the interrupt signal when the interrupt acknowledge is received by the interrupt acknowledge circuit and when the interrupt vector match is received by the vector match circuit. In so doing, the state based interrupt is transformed by the system of the present invention to a event based interrupt signal.

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Tempe, AZ, United States of America

Harold Downey