Rca Inc.

Harris Corporation

Intersil Americas Inc.

Harold Allen Wittlinger

Salomon Vulih

Stephen J Glica

Raymond L Giordano

John A Olmstead

Michael Scott Fisher

Carmine P Salerno

A voltage margin circuit has an input that receives a control voltage for programming an output reference voltage. The control voltage is coupled through an input resistor to an operational amplifier, referenced to a voltage midway between the voltage range of the input voltage and having its output coupled to a pair of transistors, whose current flow paths are coupled to inputs of a first pair of current mirrors. Outputs of the first current mirrors pair are cross-coupled to inputs of a second current mirrors pair. Outputs of the second current mirror pair are coupled through an output resistor to a prescribed voltage. The output reference voltage is the sum of the prescribed voltage and an offset as the product of the output resistor and an output current supplied by one of the third and fourth current mirrors.

Margining pin interface and control circuit

A voltage margin setting interface circuit has a single input pin, and is configured to program the slew rate and polarity direction of variation of the operation of a digital-to-analog converter, such as may be used to set a reference voltage level, for application to an error amplifier of a voltage regulator circuit of the power supply of a personal computer. A DAC clocking control circuit is coupled to an output port, and to respective DAC increment and decrement ports, and is operative to control the magnitude of output current, and to assert an output signal at one of the increment and decrement ports, in accordance with a prescribed relationship between the voltage and upper and lower ranges of the input voltage relative to its middle value.

Margining pin interface circuit for clock adjustment of digital to analog converter

An absolute value circuit includes an operational amplifier, the output of which is coupled to control inputs of complementary polarity transistors having current flow paths therethrough coupled in series with inputs of current mirror amplifier stages. A common node of the current flow paths through the transistors is coupled to an input of the operational amplifier to which a current waveform is applied. The current mirror amplifier stages are configured so as to provide like polarity output currents. The outputs of the current mirror amplifier stages are combined to produce an output current that corresponds to a full wave rectification or absolute value of an input current coupled to the operational amplifier.

Absolute value circuit

In systems embodying the invention, circuitry responsive to first and second, complementary, input signals controls the application of the input signals to a positive signal integrator and to a negative signal integrator. When the amplitude of the input signals is greater than a predetermined value, the one of the two input signals which is positive relative to the other is applied to the positive signal integrator and the other one of the two input signals is applied to the negative signal integrator. When the amplitude of the input signals is smaller than a predetermined level, the circuitry causes the periodic application of the first input signal to the positive signal integrator and the second input signal to the negative signal integrator during one time interval, and the periodic application of the first input signal to the negative signal integrator and the second input signal to the positive signal integrator during a second, subsequent, time interval of similar duration as the one time interval.

Electrical system with small signal suppression circuitry

Signals generated by a knock sensor are coupled to an electronic network for amplifying and processing the output signals of the knock sensor. The electronic network includes a device for charging a storage capacitor to a potential which is a function of the amplitude of the knock sensor output signal. The storage capacitor is coupled to the input of an amplifier via a normally closed first switch. A detector for sensing any disconnection of the knock sensor from the electronic system produces a control signal indicative of a disconnect condition. The control signal is used to open the normally closed first switch and to cause the input of the amplifier to be clamped to a reference potential which lies outside the signal range normally produced across the storage capacitor whereby the output of the output of the amplifier is placed at a predetermined level indicative of a disconnect condition. The amplifier thus produces signals at its output which are within a predetermined range during normal operation and a signal outside of this range in response to a knock sensor disconnect condition. Thus, a single line from the output amplifier carries regular normal signals and the disconnect signal lying outside the range of the normal signals.

Knock sensor system for detecting and responding to a disconnect

A comparator circuit has first and second inputs and an output and includes means for operating the comparator in alternate autozero and comparator phases. During an autozero phase, the inputs of the comparator are clamped to a reference potential and during a compare phase, input signals are applied to the input of the comparator. Control signals are applied to the inputs of the comparator during a portion of the compare phase. The control signals determine the state of the comparator output when the input signals applied to the inputs of the comparator are below a predetermined level.

Comparator with small signal suppression circuitry

A transconductance amplifier suitable for the input stage of a comparator with the capability of amplifying input signals with common mode voltage components in a range including the entirety of its operating voltage. Operation at one voltage extreme is accomplished by use of a long tailed pair connection of a pair of bulk modulated FETs with gates at the input terminals of the amplifier. Operation at the other voltage extreme is accomplished by the use of a pair of FETs in a source follower mode to drive common gate transistors of opposite polarity, the gates of the FETs also being connected to the input terminals of the amplifier. A common high impedance load for the comparator is connected to current mirrors of the drains of both pairs of FETs in the amplifier. The circuit may be implemented with bipolar transistors and additional amplification provided. Methods of comparing voltages are also disclosed.

Wide common mode range comparator and method

Two filter sections having different frequency responses are interconnected via selectively enabled switches, formed on the same integrated circuit (IC) as the filter sections, between a signal input terminal and a signal output terminal. The selectively enabled switches can be used to: (a) selectively connect the two filter sections in cascade between the signal input and output terminals to produce a bandpass filter; or (b) selectively connect the two filter sections in parallel to produce a notch filter, or (c) couple only one of the two filter sections between the signal input and output terminals; or (d) provide a short circuit between the signal input and output terminals. In a preferred embodiment the filter sections are switched capacitor filters. The filter system of the invention is highly suited for use in an engine knock signal processor integrated circuit.

Reconfigurable filter system

A Class D (audio) amplifier and method in which an input signal for the amplifier is pulse width modulated outside of the amplifier's feedback loop, and in which the pulse width modulated input signal and a pulsed signal from the feedback loop are summed in the feedback loop and fed back to the amplifier. The removal of the pulse width modulation stage and signal integration stage from the feedback loop improves distortion.

Class D amplifier and method

A transconductance amplifier suitable for the input stage of a comparator with the capability of amplifying input signal with common mode voltage components in a range including the entirety of its operating voltage. Operation at one voltage extreme is accomplished by use of a long tailed pair connection of a pair of bulk modulated FETs with gates at the input terminals of the amplifier. Operation at the other voltage extreme is accomplished by the use of a pair of FETs in a source follower mode to drive common gate transistors of opposite polarity, the gates of the FETs also being connected to the input terminals of the amplifier. A common high impedance load for the comparator is connected to current mirrors of the drains of both pairs of FETs in the amplifier. The circuit may be implemented with bipolar transistors and additional amplification provided. Methods of comparing voltages are also disclosed.

An amplifier system embodying the invention includes an input stage comprising one or more differential amplifiers having a high degree of common mode rejection. The inputs of the differential amplifiers of the input stage are AC coupled to different signal input terminals which are adapted to receive small information signals riding on large common mode signals. The AC coupling blocks any dc level associated with the input signals from affecting the amplifier system and the high degree of common mode rejection maintains the gain of the amplifiers relatively constant over a wide range of common mode signals. The outputs of the differential amplifiers of the input stage are connected in common to an output node to sum their output signals and to reduce random noise associated with the input signals and the input stage. The output node of the input stage is AC coupled to the input of a second stage whose output is in turn AC coupled to a third output stage to reduce the effect of amplifier offsets. The gain of the amplifier system is controlled by low pass filters connected to the output node of the input stage and to the output of the second stage. In certain embodiments a biasing clock is coupled via resistors to the inputs of the differential amplifiers to generate a dc bias level at their inputs which is a function of the duty cycle of the clock, the resistor connected at the input and coupling capacitor connected to the input.

Amplifier system for low level sensor signal

Signals applied to the gate of an enhancement-mode field effect transistor by resistive coupling, via a dc-blocking capacitor, are self-biased. The self biasing is carried out by detecting the signal amplitude and applying a portion of the direct voltage from this detection to the gate of the field effect transistor through the coupling resistor.

Self-biasing for enhancement-mode field effect transistors

A differential current amplifier includes a differential input transistor pair having respective first and second unity gain current mirror amplifiers (CMA) connected in their respective output circuits. The output terminal of the CMA connected in the output circuit of the first transistor of the differential pair is connected to the input terminal of the second transistor of the differential pair. The output terminal of the CMA connected in the output circuit of the second transistor is connected to the input terminal of the first transistor. The current feedback to the input terminals of the differential pair conditions them to be responsive to input signal currents. An amplifier output current can be derived from an additional current output from one of the first and second CMA's, the additional CMA output having a gain of A relative to the unity gain output.

Differential current amplifier

A bandgap reference voltage generating circuit develops a predetermined reference potential between first and second terminals. A pair of transistors are operated at different emitter current densities to develop a difference between their base-emitter potentials. That difference is applied across a first resistance and is increased and applied across a second resistance. The reference potential comprises the sum of at least the scaled-up potential and the conduction potential of a semiconductor junction. A regulating transistor completes a degenerative feedback connection and controls the current flowing between the first and second terminals responsive to the reference potential departing from the predetermined value. A regenerative feedback connection responds to the current in the regulating transistor to decrease the potential across the second resistance when the controlled current increases.

Voltage reference circuit with feedback circuit

A position sensing and display means for use on a weighing scale includes two stationary spaced conductive plates to which out-of-phase oscillations are supplied. A movable conductive plate has a position between the two stationary plates dependent on the weight of an object being measured. The amplitude of the oscillations capacitively coupled to the movable conductive plate is displayed as an indication of the weight of the object.

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Pennington, NJ, United States of America

Harold Allen Wittlinger