Universal Data Systems, Inc.

Harold A Vaghy

Keith E Atwell

Jason N Morgan

An equalizer is arranged for equalizing a received signal comprising 2-binary, 1-quaternary-coded multi-level signals S(-3), S(-1), S(+1), S(+3) corresponding to predetermined signal levels -3, -1, +1, +3, respectively. The equalizer includes a gain unit (107) with an adjustable gain, a filter (111) with an adjustable pole and zero, and a processor (119). The processor adjusts the equalizer by sampling equalized S(+3) signals and adjusting the gain, the pole and the zero so that the average value of the equalized S(+3) signals is substantially equal to +3 volts and the variance of the equalized S(+3) signals is minimized.

Adaptive equalizer method and apparatus

Errors in a predetermined digital sequence are detected by utilizing a detector which includes memory elements such as a series shift register, and logic gates for detecting a predetermined subsequence. Errors are detected by comparing each bit in the data stream with the output of the memory. Logic gates inhibit the detection of an error in response to the subsequence detection.

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Huntsville, AL, United States of America

Harold A Vaghy