Lam Research Corporation

Asml Netherlands B.v.

Harmeet Singh

Thorsten B Lill

Vahid Vahedi

Keith William Gaff

Alex Paterson

Neil M Benjamin

Keith Laurence Comendant

John C Valcore, Jr

Jeffrey S Marks

Wenbing Yang

Saurabh J Ullal

John Patrick Holland

Gowri Kamarthy

John Edward Daugherty

Bradford J Lyndaker

Richard Alan Gottscho

Peter L G Ventzek

Dennis Michael Hausmann

Samantha SiamHwa Tan

Meihua Shen

Keren Jacobs Kanarik

Taeseung Kim

Alexander Kabansky

Rajinder Dhindsa

Vadim Yevgenyevich Banine

Theodorus Petrus Maria Cadee

Saravanapriyan Sriraman

Thomas W Mountsier

Brett C Richardson

Sirish K Reddy

Joydeep Guha

Leonard John Sharpless

Aaron Eppler

Monica Titus

Kaushik Chattopadhyay

David J Cooperberg

Richard Janek

Andrew D Bailey, Iii

Richard Stephan Wise

Sander Frederik Wuister

Akira Koshiishi

Koen Jacobus Johannes Maria Zaal

Jozef Maria Finders

Roelof Koole

Emiel Peeters

Henry Povolny

Samantha S H Tan

Alan Jeffrey Miller

Frank Lin

Jason Augustino

Jun Shinagawa

Anthony L Chen

Raphael Casaes

Jeff A Bogart

Sung Lee

Shang-I Chou

Chris Lee

Prithu Sharma

Helene Del Puppo

Shibu Gangadharan

Thomas A Kamp

Douglas Ratto

Alexei Marakhtanov

Joeri Lof

Hong Shih

Andreas Fischer

Felix Leib Kozakevich

Mark W Kiehlbauch

Zhigang Chen

Sven Antoin Johan Hol

Eric A Pape

Baosuo Zhou

Duane Outka

Anthony De La Llera

Adrianus Hendrik Koevoets

Dean Jay Larson

Sang Ki Nam

Alexander Matyushkin

Jorge Luque

Travis R Taylor

Mohammad Kamarehi

Yoshie Kimura

Shenjian Liu

Christopher Kimball

Johannes Antonius Gerardus Akkermans

Yifeng Zhou

Sanket Sant

Michael S Kang

Ramin Badie

Robert G O'Neill

Petrus Theodorus Rutgers

John Hoang

David Z Carman

Peter Michel Silvester Maria Heijmans

Ole Waldmann

Richard A Marsh

Quan Chau

Seetharaman Ramachandran

Linda Fung-Ming Lee

Sam Do Lee

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Internal plasma grid for semiconductor fabrication

A substrate support for a substrate processing system includes a baseplate, a bond layer provided on the baseplate, and a ceramic layer arranged on the bond layer. The ceramic layer includes a first region and a second region located radially outward of the first region, the first region has a first thickness, the second region has a second thickness, and the first thickness is greater than the second thickness.

Electrostatic chuck with features for preventing electrical arcing and light-up and improving process uniformity

An electrostatic chuck includes an embedded electrode receiving a first voltage to electrostatically attract a semiconductor substrate to the electrostatic chuck. A plurality of current loops are disposed in at least one of the electrostatic chuck and an edge ring surrounding the electrostatic chuck. The current loops are laterally spaced apart. Each current loop is a wire formed into a loop. One or more DC power sources are electrically connected to the current loops. A controller supplies the first voltage to the embedded electrode, supplies a DC current to the current loops from the power sources, and controls the power sources. Each current loop is independently operable and generates a localized DC magnetic field proximate to the semiconductor substrate on receiving the DC current during plasma processing of the semiconductor substrate to adjust the plasma processing of the semiconductor substrate. The localized DC magnetic field does not generate plasma.

Systems and methods for correcting non-uniformities in plasma processing of substrates

A substrate support in a semiconductor plasma processing apparatus, comprises multiple independently controllable thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the thermal zones. A substrate support in which the substrate support is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the substrate support include bonding together ceramic or polymer sheets having thermal zones, power supply lines, power return lines and vias.

Substrate support with thermal zones for semiconductor processing

A plasma processing system for processing semiconductor substrates is provided. The plasma processing system includes a plasma processing volume having a volume less than the processing chamber. The plasma processing volume is defined by a top electrode, a substrate support surface opposing the surface of the top electrode and a plasma confinement structure including at least one outlet port. A conductance control structure is movably disposed proximate to the at least one outlet port and capable of controlling an outlet flow through the at least one outlet port between a first flow rate and a second flow rate. The conductance control structure controls the outlet flow rate and an at least one RF source is modulated and at least one process gas flow rate is modulated corresponding to a selected processing state set by the controller during a plasma process.

System for coordinating pressure pulses and RF modulation in a small volume confined process reactor

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

Described herein is a method of detecting fault conditions in a multiplexed multi-heater-zone heating plate for a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus.

Methods of fault detection for multiplexed heater array

Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.

Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch)

A component of a plasma processing chamber having a protective liquid layer on a plasma exposed surface of the component The protective liquid layer can be replenished by supplying a liquid to a liquid channel and delivering the liquid through liquid feed passages in the component. The component can be an edge ring which surrounds a semiconductor substrate supported on a substrate support in a plasma processing apparatus wherein plasma is generated and used to process the semiconductor substrate. Alternatively, the protective liquid layer can be cured or cooled sufficiently to form a solid protective layer.

Component of a plasma processing apparatus having a protective in situ formed layer on a plasma exposed surface

Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold.

Controlling ion energy within a plasma chamber

A tunable multi-zone injection system for a plasma processing system for plasma processing of substrates such as semiconductor wafers. The injector can include an on-axis outlet supplying process gas at a first flow rate to a central zone and off-axis outlets supplying the same process gas at a second flow rate to an annular zone surrounding the central zone. The arrangement permits modification of gas delivery to meet the needs of a particular processing regime by allowing independent adjustment of the gas flow to multiple zones in the chamber. In addition, compared to consumable showerhead arrangements, a removably mounted gas injector can be replaced more easily and economically.

Tunable multi-zone gas injection system

A component of a substrate support assembly such as a substrate support or edge ring includes a plurality of current loops incorporated in the substrate support and/or the edge ring. The current loops are laterally spaced apart and extend less than halfway around the substrate support or edge ring with each of the current loops being operable to induce a localized DC magnetic field of field strength less than 20 Gauss above a substrate supported on the substrate support during plasma processing of the substrate. When supplied with DC power, the current loops generate localized DC magnetic fields over the semiconductor substrate so as to locally affect the plasma and compensate for non-uniformity in plasma processing across the substrate.

Component of a substrate support assembly producing localized magnetic fields

A reluctance actuator assembly comprising a reluctance actuator, a flux sensor to measure a magnetic flux in a gap of the reluctance actuator, and a flux amplifier to drive an actuator coil of the reluctance actuator based on a flux set point and the flux measured by the flux sensor. A method comprising providing to the flux amplifier a flux setpoint, the flux setpoint comprising a time constant component and a sinusoidally varying component at an excitation frequency, measuring a force generated by the reluctance actuator in response to the flux setpoint, and calibrating the reluctance actuator assembly from the measured force.

Method of calibrating a reluctance actuator assembly, reluctance actuator and lithographic apparatus comprising such reluctance actuator

A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

Sub-pulsing during a state

A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.

High aspect ratio etch of oxide metal oxide metal stack

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Fremont, CA, United States of America

Harmeet Singh