International Business Machines Corporation

Kabushiki Kaisha Toshiba

Sony Computer Entertainment Inc.

Google Inc.

Harm Peter Hofstee

Sang Hoo Dhong

James Allan Kahle

Charles Ray Johns

Michael Norman Day

John Samuel Liberty

Joel Abraham Silberman

Osamu Takahashi

Brian King Flachs

Ravi Nair

Kevin John Nowka

Thuong Quang Truong

Daniel Alan Brokenshire

Michael K Gschwind

Moon Jung Kim

Daeik Daniel Kim

Karl J Duvalsaint

David William Boerstler

Mohammad Peyravian

David James Shippy

Brad William Michael

John-David Wellman

Takeshi Yamazaki

Martin Edward Hopkins

Stephen Douglas Posluszny

Mark Richard Nutter

Masakazu Suzuoki

Barry L Minor

Sumedh Wasudeo Sathaye

Erik Richter Altman

Peter George Capek

Claude Basso

Fabrice Jean Verplanken

Jean Louis Calvignac

Silvia Melitta Mueller

Colin Beaton Verrilli

Kanak Behari Agarwal

Dieter F Wendel

Eskinder Hailu

Chih-Jen Chang

David John Craft

Hwa-Joon Oh

Matthew Edward King

Brian King Flacks

Steven Douglas Posluszny

Christian Jacobi

Gordon Taylor Davis

Robert K Montoye

Shigehiro Asano

David Jones Craft

Eric A Johnson

Atsushi Kunimatsu

Peichun Peter Liu

David Meltzer

Damir Anthony Jamsek

Gordon Clyde Fossum

Yuji Suzuki

Andrew Kenneth Martin

Randall Joseph Stutzman

Pradeep Kumar Dubey

Jamil A Wakil

Peichum Peter Liu

Shoji Onishi

John Ulrich Knickerbocker

Paul Stephen Andry

Edmund Juris Sprogis

Hung Cai Ngo

Bernard Charles Drerup

Jan Van Lunteren

Michael Jay Shapiro

Maximino Aguilar, Jr

Hans-Werner Tast

Michael Fan Wang

Barry Joe Wolford

Jeffrey Douglas Brown

Chirag Suryakant Patel

Jens Leenstra

Thomas W Keller, Jr

Mark A Johnson

Bishop Chapman Brock

Akiyuki Hatakeyama

George A Katopis

Matthew E Fernsler

Wendel Glenn Voigt

Sam Dinkin

Jaehong Park

Ramyanshu Datta

Paula Kristine Coulman

Zoltan Szlavik

Alexander S J Misdorp

Micahel Norman Day

Chekib Akrout

T c/o Sony Computer Ent America Inc Yamazaki

M c/o Sony Computer Entertainment Inc Suzuoki

Shigehiro c/o KK Toshiba Asano

Atsushi c/o KK Toshiba Kunimatsu

Martin E Hopkins

Masakazu Sony Computer Ent Inc Suzuoki

Atsushi c/oKabushiki Kaisha Toshiba Ipd Kunimatsu

A method, computer program product and computer system for trusted timestamping is provided. A processor generates a first key pair, where the key pair includes a public key and a private key. A processor publishes the public key of the first key pair to an immutable data structure. A processor receives a first digital file for timestamping. A processor signs the first digital file with the private key of the first key pair.

Trusted timestamping

A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

Configurable interface controller

A generic microprocessor architecture is provided with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Virtualization across physical partitions of a multi-core processor (MCP)

A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Multithreaded programmable direct memory access engine

The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.

Security architecture for system on chip

A mechanism is provided for dictionary matching. The mechanism loads a plurality of dictionary memory arrays with a set of dictionary words and updates a plurality of status arrays. Each status array of the plurality of status arrays corresponds to a respective one of the plurality of dictionary memory arrays. Each entry of a given status array stores a status bit, which indicates whether a corresponding entry of the corresponding dictionary memory array stores a valid dictionary word. The mechanism receives an input data word and generates a hash value based on the input data word. The mechanism reads a dictionary word from each of the dictionary memory arrays and a status bit from each of the status arrays using the hash value as a read address. The mechanism determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word.

High speed large scale dictionary matching

Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

High bandwidth decompression of variable length encoded data streams

This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Virtualization in a multi-core processor (MCP)

Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.

Authenticating messages using cryptographic algorithm constants supplied to a storage-constrained target

A processor system executes multiple applet programs within a software application program in an information handling system. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In particular, the operating system software manages partitioning of a register file in the processor system to achieve a cooperative relationship among multiple applet programs within respective partitions of the register file. In one embodiment, the operating system software manages unique applet ID's to modify register file partition sizes and locations during applet program instruction text execution. In one embodiment, applet ID masking hardware provides sharing of register file space among multiple copies of applet program code.

Method and apparatus for cooperative software multitasking in a processor system with a partitioned register file

The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Main processing element for delegating virtualized control threads controlling clock speed and power consumption to groups of sub-processing elements in a system such that a group of sub-processing elements can be designated as pseudo main processing element

This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries.

Delegated virtualization across physical partitions of a multi-core processor (MCP)

A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

Silicon carrier structure and method of forming same

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Austin, TX, United States of America

Harm Peter Hofstee