Intel Corporation

Harishankar Sridharan

Jacob Schneider

Navneet Dour

Roger K Cheng

James E Jaussi

Aaron K Martin

Nasser A Kurd

Christopher P Mozak

Andrew M Volk

Hing Yan To

Praveen Mosalikanti

Mozhgan Mansuri

Robert R Fulton

Ritesh B Trivedi

Chinnugounder Senthilkumar

Tea M Lee

Hariprasath Venkatram

Hsien-Pao Yang

Mohammed G Mostofa

Karthik Tyamgondlu

Pavan Kumar Kappagantula

Satish Krishnamoorthy

Senthilkumar Ganapathy

Pushkar Gorur

Rajesh Inti

An apparatus is provided, where the apparatus includes a first transistor coupled between a supply node and an output node; a resistor and a second transistor coupled in series between the output node and a ground terminal; a circuitry to receive data, and to output a first control signal and a second control signal to respectively control the first transistor and the second transistor, wherein an output signal at the output node is indicative of the data, and wherein the first transistor is a N-type transistor.

Transmitter circuitry with N-type pull-up transistor and low output voltage swing

An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Dual power I/O transmitter

Disclosed embodiments may include a circuit having a clock-to-output (TCO) compensation circuit coupled to a RAM pull-up transmitter and a RAM pull-down transmitter. The TCO compensation circuit may be configured to compare a first output with a second output and to generate a delay code, based on the comparison, for at least one other RAM transmitter on the die to adjust a duty cycle of a third output associated with the at least one other RAM transmitter. Other embodiments may be disclosed.

Duty cycle compensation of RAM transmitters

Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.

Method and apparatus for fast wake-up of analog biases

Provided herein are approaches for controlling remote slave DLL circuits with a master DLL circuit by conveying a relevant bias signal as a current signal instead of as a voltage signal.

Bias signal delivery

Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be 'awoken' (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.

Wake-up circuit

An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.

Calibrating integrating receivers for source synchronous protocol

A circuit for producing a reliable duty cycle for a low power oscillator. The circuit produces a square wave signal based on the differences between the oscillating output signal driven by a piezoelectric crystal and a phase shifted output signal. This circuit provides a quick start for a clock signal, generates a reliable fifty percent duty cycle and is better protected from common mode noise. This circuit can also be configured to be programmable to provide for an adjustable duty cycle.

Duty cycle tuner for low power real time clock oscillator

Growing community of inventors

Folsom, CA, United States of America

Harishankar Sridharan