Texas Instruments Corporation

Harish Venkataraman

Vadim Valerievich Ivanov

Susan A Curtis

Karan Singh Jain

Myron J Koen

Erick Omar Torres

Daniel A King

Philomena Cleopha Brady

Timothy Bryan Merkin

Byungchul Jang

Jim Le

An inductor conducts a first current, which is variable. A first transistor is coupled through the inductor to an output node. The first transistor alternately switches on and off in response to a voltage signal, so that the first current is: enhanced while the first transistor is switched on in response to the voltage signal; and limited while the first transistor is switched off in response to the voltage signal. A second transistor is coupled to the first transistor. The second transistor conducts a second current, which is variable. On/off switching of the second transistor is independent of the voltage signal. Control circuitry senses the second current and adjusts the voltage signal to alternately switch the first transistor on and off in response to: the sensing of the second current; and a voltage of the output node.

Method and circuitry for sensing and controlling a current

A method is provided. A first reference voltage during an idle mode is selected, and the first reference voltage is applied to a switched-mode converter. A first output voltage is then generated by the switched-mode converter from a power supply, and a capacitor is overcharged with the first output voltage. The first output voltage is regulated to generate a second output voltage during the idle mode. Then, a second reference voltage during a quiet mode, where the second reference voltage to the buck converter. During the quiet mode, a third output voltage is generated from the switched-mode converter and from discharging the overcharged capacitor, and the third output voltage is regulated to generate the second output voltage.

Power management system and method with adaptive noise control

A bandpass sense amplifier circuit (FIG.A) is disclosed. The circuit includes a capacitor (C) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (-) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit () has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.

Capacitor, first and second current conveyors mirror current into input

Low noise capacitive sensor with integrated bandpass filter

A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, R, and feedback capacitor, C, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, Rand Rand wherein the other side of the feedback capacitor is coupled between Rand the output of the first amplifier, Ris connected to Vfrom one side and Rand Rfrom the other, Ris connected to Rand Rfrom one side and Cand output of the first amplifier from the other side, another resistor, Ris connect to the output of the first amplifier, Cand Rfrom one side and Ryet another resistor, and input of ampfrom the other, a second amplifier, Ampis connected to the Rand Rat one input and 1.5v at the other input, and wherein the output of the second amplifier is connected to Rand Rconnects to one input of the second amplifier and the output of the second amplifier.

Method, apparatus and system for level shifting of common mode voltage from input to output for capacitive feedback transimpedance amplifier

A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

Low-loss step-up and step-down voltage converter

An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.

Integrated receiver and ADC for capacitive touch sensing apparatus and methods

A circuit includes an input stage configured to receive a regulated input signal and generate an input stage output signal in response to the regulated input signal. An isolation stage can be configured to pass the input stage output signal to a buffered output node. The isolation stage receives feedback from the buffered output node to deactivate the buffer input stage if transient voltages are generated at the buffered output node. An output stage can be configured to provide current to the buffered output node in response to the regulated input signal.

Unidirectional output stage with isolated feedback

Circuitry (-) for limiting the maximum amount of current (I) flowing through a first electrode (DRAIN) of a first transistor (T) includes an amplifier () having an output coupled by a conductor () to a control electrode of the first transistor and limiting circuitry () including reference current sensing circuitry (,T) having a reference current source (I). A reference current sensing transistor (T) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal () of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Current limiting circuitry and method for pass elements and output stages

A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter.

Fast startup algorithm for low noise power management

A voltage regulator controls a regulated output voltage (Vout) by feeding it back to a differential input stage () receiving a reference voltage (Vref) and applying an output () to a control electrode of a follower transistor (M) that is coupled to an output stage () which generates the output voltage (Vout). The output stage operates pull-up (MB) and pull-down (MB) transistors in response to a signal (A) produced by the follower transistor (M) during normal regulation operation, and provides fast settling of the output voltage by turning on a transient pull-up transistor (MA) or transient pull-down transistor (MA) in response to the signal (A) produced by the follower transistor (M) during a fast increasing or decreasing transition, respectively, of the load current (I). A filtering resistor (R) is coupled between the output voltage and a common electrode of the transient pull-up and pull down transistors.

Low noise voltage regulator and method with fast settling and low-power consumption

A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.

Fast-settling precision voltage follower circuit and method

A comparator () includes a first input transistor (M) having a drain coupled to a gate and drain of a first diode-connected transistor (M) and a gate of a first current mirror output transistor (M), and a second input transistor (M) having a drain coupled to a gate and drain of a second diode-connected transistor (M) and a gate of a second current mirror output transistor (M). Sources of the first and second current mirror output transistors are connected to a supply voltage (V). Gates of the first and second input transistors are coupled to first (V) and second (V) input signals, respectively. Sources of the first and second diode-connected transistors are coupled to drains of the first and second current mirror output transistors, respectively. A latch circuit (M,M) is coupled to the drains of the first and second current mirror output transistors.

Comparator and method with adjustable speed and power consumption

A programmable gain low noise amplifier includes a tail current transistor (Q) having a source coupled to a first reference voltage (VDD) and a drain coupled to a tail current conductor () and, in a differential input embodiment, a plurality of pairs (Q, QQ, Q) of differentially coupled input transistors. Each pair includes a first input transistor having a gate coupled to a first input conductor (A) and a drain coupled to a first output conductor (A) and a second input transistor having a gate coupled to a second input conductor (B), a source coupled to a source of the first transistor, and a drain coupled to a second output conductor (B). The sources of the first and second input transistors of some or all of the pairs are selectively coupled to the tail current conductor () in it response to corresponding gain control signals (B).

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Wylie, TX, United States of America

Harish Venkataraman