Maxim Integrated Products, Inc.

Ambarella, Inc.

Harish S Muthali

Kourosh Pahlavan

Xiaojun Zhu

Elik E Cohen

Ari Vauhkonen

Charles John Razell

Systems, devices and methods are disclosed for an ultra-wide-band (UWB) transmitter tag capable of operating in different power mode depending on voltage level and/or host interruption signal. The transmitter tag comprises a power management circuit, a one-time-programmable memory (OTP), a read/write memory, a state machine for controlling/monitoring the operation of the tag. The tag goes into the high power mode when the power supply ramps up to a preset voltage level. During the high power mode, the tag consumes the higher level of electrical current as indicated by the battery current signal. Upon completion of high power consumption activity, such as OTP memory download, the tag exits the high power mode and enters the low power mode. The power supply current goes to the low level to minimize the power consumption by the tag.

Low power ultra-wide-band transmitter

Systems, devices and methods are disclosed using a transmitter architecture to keep the transmitter in a deep sleep mode before activation/enabling. The transmitter tag comprises a power-good-detector, a first regulator and a second regulator. The power-good-detector includes a power-good-latch, a ring oscillator and a ripple counter. Upon disconnecting a GPIO pin from the ground, the power-good-latch sends a Bias_EN signal to the regulator. Upon receipt of the Bias_EN signal, the first regulator transmits a wakeup signal to the ring oscillator, which then starts sending the clock signals to the ripple counter. When the counted clock signals reach a threshold value, the ripple counter sends the power-good-digital signal to the flip flops. When the tag is in the reset mode, the power-good-digital signal is also low. When the power-good-digital signal goes from low to high, the tag is out of the reset mode.

Power-good detector for ultra-wide band transmitter with emphasis on low power consumption

An apparatus comprising a first phase circuit, a second phase circuit, and a current steering circuit. The first phase circuit may be configured to generate a first portion of a phase interpolated clock signal in response to (i) a control signal, (ii) a first bias signal, and (iii) a feedback of said phase interpolated clock signal. The second phase circuit may be configured to generate a second portion of the phase interpolated clock signal in response to (i) the control signal, (ii) a second bias signal, and (iii) the feedback of the phase interpolated clock signal. The current steering circuit may be configured to generate the first bias signal and the second bias signal in response to a reference bias signal.

Low supply voltage analog phase interpolator

An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.

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San Jose, CA, United States of America

Harish S Muthali