Cisco Technology, Inc.

Lilac Cloud, Inc.

Greenfield Networks, Inc.

Harish Ramamurthy Devanagondi

Simon Luigi Sabato

Jay S Shah

Harish P Belur

Brian Arnold Petersen

Rajesh Patil

Jui-Yang Lu

Srikanth Lakshminarasimhan

James P Rivers

Richard John Heaton

Hugh Barrass

David M Smith

Sanjeev Mahalawat

You-Wen Yi

Adam Goldstein

Kamran Torabi

Jianyong Sun

Majid Torabi

Sheausong Yang

Krishna Kumar Vavilala

James Sun

Jasper Yeung

Nicholas Bambos

Ramesh Yarlagadda

Shwetal Desai

Umesh Kumar Muniswamy

In an embodiment, content data delivery to a requesting device in a content delivery network (CDN) may be handled by a server device using a content cache of a computing device associated with the server device. The computing device may be a component of, local to, and/or directly connected to the server device. The server device receives a request to deliver the content data, determines that the location of the content data is in the content cache, and responsive to this determination, sends instructions to the computing device to provide the content data to the requesting device. In one embodiment, the server device may acquire and provide the content data to the computing device for storage in the content cache, before or in response to receiving the request to deliver the content data.

Application cache acceleration using device content cache

In an embodiment, application delivery to end-user devices may be handled by a combination of an application device and a distributed set of split edge devices located closer to the end-user device within a network. The split edge devices are instructed by the application device about how to manage traffic to and from the end-user devices. The application device determines whether content is stored to content cache of a split edge device. The application device, when the content is stored to the split edge device, refrains from sending the content and instead sends instructions to the split edge device that include reference to a location of the content, and instruct the split edge device to send the content to an application and/or device. The application device, when the content is not stored to the split edge device, sends the content with instructions to store the content locally.

Distributed split edge application architecture

In an embodiment, responsive to determining: (a) a first command is not of a particular command type associated with one or more hardware modules associated with a particular routing node, or (b) at least one argument used for executing the first command is not available: transmitting the first command to another routing node in the hardware routing mesh. Upon receiving a second command of the command bundle and determining: (a) the second command is of the particular command type associated with the hardware module(s), and (b) arguments used by the second command are available: transmitting the second command to the hardware module(s) associated with the particular routing node for execution by the hardware module(s). Thereafter, the command bundle is modified based on execution of the second command by at least refraining from transmitting the second command of the command bundle to any other routing nodes in the hardware routing mesh.

Command-aware hardware architecture

In an example embodiment, a technique for network based power management for power consuming devices associated with a network. A power control strategy is communicated to network elements coupled to the network. The power control strategy is enforced by the network elements and the network elements report power consumption. Each network element enforces the power strategy relative to the set of power consuming devices operatively associated with the network element. Groups of subtended network elements can manage the power policy in a cluster power management mode or in a collaborative cluster management mode.

Network based system to control and monitor power consumption of networked elements

The disclosure describes queue management based on queue sets. A queue set comprises a group of packets or packet references that are processed as a single entity or unit. For example, when a queue set reaches the head of a queue in which it is stored, the entire queue set including its packets or packet references is passed for scheduling as a single unit. A queue set provides the benefit of a single operation associated with enqueuing and a single operation associated with dequeuing. Since only one operation on a queue is required for the typical case of several packets in a queue set rather than for every packet, the rate of queue operations may be significantly reduced. A queue set has a target data unit size, for example, a roughly equal number of packet bytes represented by each queue set, regardless of the number of packets referenced by a queue set. This means that a scheduler of a queue manager, which is tasked with metering the number of packet bytes transmitted from each queue per time unit, is provided with a list of packets which represents a predictable quantity of packet bytes, and this predictability streamlines the scheduling task and significantly reduces the number of operations.

System and method for queue management using queue sets

A network switch having a hybrid switch architecture, which is scalable to increase connectivity, buffering, and bandwidth by using multiple shared-memory switch fabrics and multiple crossbar switch fabrics. Each of the crossbar switch fabrics is coupled to each of the shared-memory switch fabrics. The shared-memory switch fabrics are configured to store and retrieve packets. The crossbar switch fabrics are configured to distribute and recollect packets to and from each of the shared-memory switch fabrics. The network switch having a hybrid switch architecture distributes packets from a crossbar switch fabric to the multiple shared-memory switch fabrics to share the distributed packets among the multiple shared-memory switch fabrics.

Network switch having a hybrid switch architecture

Enhanced switching functionality is achieved by a switching system having of traffic management devices connected with a generic Ethernet switch fabric and an optional flow control device. The traffic management devices use an encapsulated Ethernet frame format to provide an additional of addressing.

Ethernet switch fabric interface

A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for processing data packets, each of the data packets being processed having an associated exception map in a memory of the apparatus. An exception detector at each processing stage detects whether any exception conditions apply to the data packet at the processing stage, and if so, a bit setter sets, modifies, or resets one or more bits in the exception map associated with exception conditions detected at the processing stage. An exception handler processes the exception map in response to the state of in the exception map after all the processing stages are complete.

Method and apparatus for unified exception handling with distributed exception identification

A multi-slice network processor processes a packet in packet slices for transfer over a multi-port network interface such as a switch fabric. The network processor segments a packet into cells having a target size. A group of cells of a common packet form a packet slice which is independently processed by one of a number of parallel processing and storage slices. Load balancing may be used in the selection of processing slices. Furthermore, the network processor may load balance slices across the multi-port network interface to one or more destination slices of another network processor. The multi-slice processor uses post header storage delivery on ingress processing to the multi-port interface thereby reducing temporary storage requirements. The multi-slice network processor may also utilize sequence numbers associated with each packet to ensure that prior to transmission onto a destination network, the packet is in the correct order for a communication flow.

Multi-slice network processor

A parallel packet processing queueing architecture and method are described. A packet is divided up into cells. A first or start processor queue is selected for the first cell. The following cells of the packet are then placed in the queues in a predetermined order. An example of a predetermined order is placing the cells in consecutive processor queues modulo (the number of processor queues) after the start processor. Such a predetermined order is illustrated in the context of a per Cell Contiguous Queueing (CCQ) architecture. The architecture provides benefits of alleviating the pre-processing and post-processing buffering burdens and decreasing the amount of information required for reassembly of the packet.

Queueing architecture and load balancing for parallel packet processing in communication networks

The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet processor. A data word in partitioned into data segments which are stored in the plurality of banks in accordance with an access scheme that hides pre-charging of rows behind data transfers. A storage distribution control module is communicatively coupled to a memory comprising a plurality of storage request queues, and a retrieval control module is communicatively coupled to a memory comprising a plurality of retrieval request queues. In one example, each request queue may be implemented as a first-in-first-out (FIFO) memory buffer. The plurality of storage request queues are subdivided into sets as are the plurality of retrieval queues. Each is set is associated with a respective DRAM device. A scheduler for each respective DRAM device schedules data transfer between its respective storage queue set and the DRAM device and between its retrieval queue set and the DRAM device independently of the scheduling of the other devices, but based on a shared criteria for queue service.

High bandwidth memory management using multi-bank DRAM devices

An architecture for a multi-port switching device is described having a very regular structure that lends itself to scaling for performance speed and a high level of integration. The distribution of packet data internal to the chip is described as using a cell-based TDM packet transport configuration such as a ring. Similarly, a method of memory allocation in a transmit buffer of each port allows for reassembly of the cells of a packet for storage in a contiguous manner in a queue. Each port includes multiple queues. The destination queue and port for a packet is identified in a multi-bit destination map that is prepended to the start cell of the packet and used by a port to identify packets destined for it. The architecture is useful for a single-chip multi-port Ethernet switch where each of the ports is capable of 10 Gbps data rates.

Single-chip multi-port Ethernet switch

A network switch having a hybrid switch architecture, which is scalable to increase connectivity, buffering, and bandwidth by using multiple shared-memory switch fabrics and multiple crossbar switch fabrics. Each of the crossbar switch fabrics is coupled to each of the shared-memory switch fabrics. The shared-memory switch fabrics are configured to store and retrieve packets. The crossbar switch fabrics are configured to distribute and re-collect packets to and from each of the shared-memory switch fabrics. The network switch having a hybrid switch architecture distributes packets from a crossbar switch fabric to the multiple shared-memory switch fabrics to share the distributed packets among the multiple shared-memory switch fabrics.

Growing community of inventors

Saratoga, CA, United States of America

Harish Ramamurthy Devanagondi