Intel Corporation

Harish Kumar

Zhongying Zhang

Brent E Lince

Herbert H Hum

Douglas M Carmean

Derek T Bachand

Michael D Upton

Chinna B Prudvi

Paul D Breuder

Aravindh Baktha

Ks Venkatraman

Quinn W Merrill

Mike D Upton

A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.

Method and apparatus for handling locks

A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled &ldquo;SLIME.&rdquo; The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the data's dirty status. The data eviction method includes storing data in a cache, storing a status field in association with the data, the status field having a first sub-field to indicate whether the data is dirty and a second sub-field to indicate whether the data is shared, when the data is to be evicted from the cache, testing the first sub-field field to determine whether the data is dirty and, if so, writing the data to another cache before evicting the data from the cache. The multi-layer cache system includes first and second caches provided in a layered arrangement with the second cache being in a higher layer than the first cache, each cache including cache entries adapted to store data and status fields associated with the data, the status field representing the state of the data, eviction logic in the first cache adapted to test the status field of a cache entry, and control logic adapted to output the contents of the cache entry to a cache entry in the second cache when the status field indicates that data in the cache entry is dirty.

&ldquo;SLIME&rdquo; cache coherency system for agents with multi-layer caches

A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.

Method and apparatus for lock synchronization in a microprocessor system

Growing community of inventors

Portland, OR, United States of America

Harish Kumar