Intel Corporation

Harish Krishnamurthy

Krishnan Ravichandran

Nachiket Venkappayya Desai

Suhwan Kim

Xiaosen Liu

Khondker Z Ahmed

Vivek K De

Vaibhav Vaidya

Christopher Schaef

Sriram R Vangal

Turbo Majumder

Fabrice Paillet

Annabelle Pratt

George Matthew

Ruchir Saraswat

Ramnarayanan Ram Muthukaruppan

Pradipta Patra

Uday Bhaskar Kadali

Mohit Verma

Sheldon Weng

Mark T Bohr

Nicholas Paul Cowley

Wilfred Gomes

Rajesh Kumar

Doug B Ingerly

Pavan Kumar

Wayne Proefrock

Scott Chiu

Gene A Frederiksen

Cary Renzema

James Keith Hodgson

Anand Ramasundar

Sally Safwat Amin

Claudia Patricia Barrera Gonzalez

Jing Han

Rajasekhara Madhusudan Narayana Bhatla

Telesphor Kamgaing

Valluri Ramana Rao

Sanu K Mathew

Tanay Karnik

Stephen H Gunther

Raghavan Kumar

Vikram B Suresh

Eugene Gorbatov

William J Lambert

Krishna Bharath

Alexander Uan-Zo-Li

Willem M Beltman

David Arditti Ilitzky

Michael Zelikson

Tomm Aldridge

Andre Schaefer

Alexander Lyakhov

Mark L Neidengard

Sameer Shekhar

Huong T Do

Ankit Prakash Gupta

Philip R Lehwalder

Jessica Gullbrand

Arik Gihon

Sergio Carlo Rodriguez

Nimrod Angel

Patrick K Leung

Dileep J Kurian

Sriram Kabisthalam Muthukumar

Bharani Thiruvengadam

Nicolas Butzen

Vishram Shriram Pandit

Karthik Sankaranarayanan

Andreas Duevel

Tamir Salus

Po-Cheng Chen

Christopher J Mandic

Xun Sun

Uwe Zillman

Taesik Na

Akhila M

Arvind Raghavan

Jason Muhlestein

Anuj Modi

Sergio Carlo

James Alexander Darnes

An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.

DVR with pulsed control and gradual NLC

An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.

Voltage regulator with binary search and linear control

A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.

Computational current sensor

Techniques and mechanisms for determining a mode of operation of a switched capacitor voltage regulator (SCVR). In an embodiment, a controller supports multiple modes of operation of the SCVR, wherein the modes each correspond to a different respective sequence of switch states of a converter core of the SCVR. One of the modes is to provide boost voltage regulation with the SCVR. The controller transitions seamlessly and autonomously between two modes based on respective reference switch states of the two modes. In another embodiment, a mode transition is performed based on a signal which a control sensor generates based on a rate of switch events of the voltage regulator, and predetermined reference information indicating current characteristics of the voltage regulator.

Device, system and method to determine an operational mode of a continuous capacitive voltage regulator

Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.

Package embedded magnetic power transformers for SMPS

Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

Device, system and method for providing inductor structures

A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.

Self-calibrated input voltage-agnostic replica-biased current sensing apparatus

A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.

Variable-adaptive integrated computational digital low dropout regulator

A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

Seamless non-linear voltage regulation control to linear control apparatus and method

A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

Non-linear clamp strength tuning method and apparatus

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Digital linear regulator clamping method and apparatus

Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

Multiple output voltage conversion

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Hillsboro, OR, United States of America

Harish Krishnamurthy