Cavium, Inc.

Marvell Asia Pte., Ltd.

Cavium International

Harish Krishnamoorthy

Gerald Schmidt

Tsahi Daniel

Anh T Tran

Guy Hutchison

Vishal Anand

Nimalan Siva

Mohan Balan

Kishore Badari Atreya

Vadana Desai

Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system.

Apparatus and method of generating lookups and making decisions for packet modifying and forwarding in a software-defined network engine

A multicast rule is represented in a hierarchical linked list with N tiers. Each tier or level in the hierarchical linked list corresponds to a network layer of a network stack that requires replication. Redundant groups in each tier are eliminated such that the groups in each tier are stored exactly once in a replication table. A multicast replication engine traverses the hierarchical linked list and replicates a packet according to each node in the hierarchical linked list.

Hierarchical hardware linked list approach for multicast replication engine in a network ASIC

An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

Apparatus and a method of detecting errors on registers

Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

Method of implementing a network ASIC in a network device

A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a mirror destination linked list are forwarded to the multicast replication engine. The mirror destination linked list typically defines a rule for mirroring. The multicast replication engine mirrors the packet according to the mirror destination linked list and the mirror bit mask vector.

Session based packet mirroring in a network ASIC

A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the enabled link in the list of links.

Fast hardware switchover in a control path in a network ASIC

Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.

Multiple-interrupt propagation scheme in a network ASIC

A testbench, including a verification environment, tests a device under test (DUT). A packet tracking module, which is verification environment agnostic, is configured to track packets in the verification environment. The packet tracking module maintains an associative data structure of packet identifiers that are indexed by a unique value, a counter for identifying the packets in the verification environment, and a set of routines for tracking the packets in the verification environment during different stages of the testing.

Packet tracking in a verification environment

A new approach is proposed which contemplates system and method for configuring a plurality of configurable registers in a programmable digital processing engine of a network device. Under the proposed approach, one or more slave configuration controllers (SCC) are utilized to configure a large number of configurable registers in a programmable engine, wherein each SCC is used to configure a plurality of configurable registers, which are organized in multiple configuration groups. The configurable registers in each configuration group are connected in a looped one-way daisy chain. During its operation, each of the slave configuration controllers is configured to receive instructions from a user via a master configuration controller (MCC), performs read or write operations on the configurable registers of one of the configuration groups as designated by the instructions from the user. Here, each of these configurable registers is equipped with an error-detecting circuit to detect dynamic soft errors; and any detected error is promptly reported back to the user through its SCC and the corresponding MCC so that the user is aware of the error at run-time.

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San Jose, CA, United States of America

Harish Krishnamoorthy