Cadence Design Systems, Inc.

Harindranath Parmeswaran

Naresh Kumar

Ratnakar Goyal

In one embodiment of the invention, a method of analysis of a circuit design is disclosed to generate a statistical timing model. The method includes receiving a timing graph of a circuit including arcs with a statistical function of delay, slew, or arrival time; determining primary input ports and output ports of the circuit; identifying timing pins between the input ports and the output ports of the circuit; and evaluating the timing pins from input ports to output ports to reduce the timing graph to ease analysis of the reduced timing graph with a processor.

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Uttar Pradesh, India

Harindranath Parmeswaran