Cadence Design Systems, Inc.

Harindranath Parameswaran

Pardeep Juneja

Henry K Yu

Sachin Shrivastava

Sanjib Ghosh

Roland Ruehl

Elias Lee Fallon

Regis R Colwell

Hui Xu

Yinnie Lee

Joshua Alexander Baudhuin

Timothy Rosek

Harsh Deshmane

Anjna Khanna

Simon Simonian

Donald John O'Riordan

Chayan Majumder

Om Kanwar

Sanjiib Ghosh

Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.

Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints

Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.

Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layout

A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.

Method and apparatus for derived layers visualization and debugging

In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more timing arcs to reduce the number of simulations to characterize the subcircuit.

Accelerated characterization of circuits for within-die process variations

Display of measurements in a graphical design on a computer system. In one aspect, shapes are displayed in an image, and a definition of a defined area of the image is received. One or more measurements are determined for one or more of the shapes displayed within the predefined area, the one or more measurements determined automatically without a user designating endpoints for the measurements. The one or more measurements are displayed as being associated with the one or more shapes.

Generation, display, and manipulation of measurements in computer graphical designs

Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.

Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness

Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.

Netlist partitioning for characterizing effect of within-die variations

An apparatus and method for reporting design rule violations of an integrated circuit design includes collecting data from a design rule checker module, processing the data, and displaying design rule violations onto the layout. The display of the design rule violations may be interactive by including hypertext links to specifications, text bubbles with violation explanations, measurements, highlighting areas of the layout corresponding to a particular rule, and providing hierarchically expandable nodes for constraint violations in a browser.

Method and apparatus for design rule violation reporting and visualization

A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.

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Noida, India

Harindranath Parameswaran