Intel Corporation

Tahoe Research, Ltd.

Harinarayanan Seshadri

Rajeev D Muralidhar

Vishwesh M Rudramuni

Youvedeep Singh

Noor Mubeen

Richard Quinzio

Christophe Fiat

Aymen Zayet

Illyas M Mansoor

Barnes Cooper

Bruce L Fleming

Sujith Thomas

Nithish Mahalingam

Rushikesh S Kadam

Tsung-Yuan Charles Tai

Ren Wang

Jr-Shian Tsai

Mesut A Ergin

Shravan Kumar Belagal Math

Suketu R Partiwala

Nivedha Krishnakumar

Christian Maciocco

Alexander W Min

Prakash N Iyer

Phil C Cayton

Arlin R Davis

Vijayakumar Ashok Dibbad

Satish Prathaban

Srividya Karumuri

Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Power governance of processing unit

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Platform power consumption reduction via power state switching

Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

Detection of known workload patterns

Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

Hardware apparatuses and methods to perform transactional power management

Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.

Systems, methods and devices for dynamic power management of devices using game theory

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., Six) instead of a second low power consumption state (e.g., S) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.

Voltage regulator efficiency-aware system energy management

Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.

Dynamically entering low power states during active workloads

Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.

Framework for runtime power monitoring and management

Growing community of inventors

Bengaluru, India

Harinarayanan Seshadri