Qualcomm Incorporated

Harikrishna Chintarlapalli Reddy

Rakesh Kumar Sinha

Alvin Leng Sun Loke

Sajin Mohamad

Pradeep Kumar Sana

Abhinav Murali

Jonathan Holland

Jibu Varghese K

Chulkyu Lee

Jeffrey Charles Lee

An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

Bias current receiver with selective coupling circuit

An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.

Thin-film resistors with flexible terminal placement for area saving

An integrated circuit, comprising a transistor-based cell comprising a set of fin field effect transistors (Fin FETs) chained together in a first direction, wherein the set of Fin FETs include fins extending longitudinally along the first direction and equally-spaced apart in a second direction orthogonal to the first direction by a fin pitch, and a set of polysilicon gates extending longitudinally along the second direction and equally-spaced apart in the first direction by a poly pitch, wherein a first dimension of the transistor-based cell along the first direction is substantially a first integer multiplied by the poly pitch, and wherein a second dimension of the transistor-based cell along the second direction is substantially a second integer multiplied by the fin pitch. The integrated circuit may include other non-transistor-based cells (e.g., passive cells), such as thin-film resistor or capacitor cells, which are arranged in a two-dimensional array with the transistor-based cell.

Analog-mixed signal circuit cells with universal Fin pitch and poly pitch

An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mlayer power interconnects coupled to a first voltage, a first set of Mlayer interconnects, a second set of Mlayer power interconnects coupled to a second voltage source, and a second set of Mlayer interconnects. The first set of endcap cells includes first and second sets of Mlayer interconnects. The first set of Mlayer interconnects is coupled to the first set of Mlayer power interconnects and to the second set of Mlayer interconnects to provide a first set of decoupling capacitors. The second set of Mlayer interconnects is coupled to the second set of Mlayer power interconnects and to the first set of Mlayer interconnects to provide a second set of decoupling capacitors.

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Bengaluru, India

Harikrishna Chintarlapalli Reddy