Intel Corporation

Harikrishna B Baliga

Peter J Smith

Lokpraveen B Mosur

Joydeep Ray

Subramaniam M Maiyuran

Salvador Palanca

Bharat S Pillilli

Ilhyun Kim

Shlomi Alkalay

Mongkol Ekpanyapong

Michael S Yu

Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.

Frequency selection granularity for integrated circuits

Techniques for controlling alignment of conditions between modular functional blocks in an integrated circuit having a hierarchical network of modular functional blocks. The output of each functional block can be logically determined by its external inputs combined with internal state feedback and internal state and is derived from a pattern of prior external inputs. Alignment of output conditions from independent and interdependent functional blocks within the hierarchical network of functional blocks is induced to provide unique conditions by modifying internal state and timing alignments with internal data and internal controls within one or more of the modular functional blocks. Functional outputs from one or more of the modular functional blocks can be monitored based on the modified internal state and timing alignments. Pattern results can be generated based on the monitoring. Test results based on the pattern results can be stored.

Alignment of microarchitectural conditions

A method and apparatus for tracking temporal use associated with cache evictions to reduce allocations in a victim cache is disclosed. Access data for a number of sets of instructions in an instruction cache is tracked at least until the data for one or more of the sets reach a predetermined threshold condition. Determinations whether to allocate entry storage in the victim cache may be made responsive in part to the access data for sets reaching the predetermined threshold condition. A micro-operation can be inserted into the execution pipeline in part to synchronize the access data for all the sets. Upon retirement of the micro-operation from the execution pipeline, access data for the sets can be synchronized and/or any previously allocated entry storage in the victim cache can be invalidated.

Tracking temporal use associated with cache evictions

An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache memory. The list structure allows for access to a relatively small store of data to determine whether or not a cache entry needs to be written to the main memory. Choosing the format of the list structure, allows one to make tradeoffs between area needed on a chip and the amount of efficiency in the cache flushing process.

List based method and apparatus for selective and rapid cache flushes

A method and apparatus for single cycle, cache line invalidation within a cache memory is described. The method includes enabling memory cells within a cache state array of the cache memory. An invalid state is then written to each memory cell within the cache state array of the cache memory. The enabling of the memory cells within the cache state array of the cache memory occurs during a first phase of a clock cycle. While the writing of the invalid state to each memory cell within the cache state array of the cache memory occurs during a second phase of the clock cycle. Consequently, cache line invalidation of each cache line within the cache memory occurs within a single clock cycle formed by the first phase of the clock cycle and the second phase of the clock cycle. In partial invalidation of the cache memory is possible by way-subdividing the cache state array or set-subdividing the cache state array. One shot or single cycle cache line invalidation reduces the total time required for invalidation of all cache lines within the cache memory to just a clock cycle. The implementation is simple with minimal changes to the cache array limited only to those cells that store the state information of the cache lines. Since many system operations necessitate invalidation of the entire cache, one-shot invalidation clearly improves the system performance with no significant impact on the die size.

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Folsom, CA, United States of America

Harikrishna B Baliga