Chartered Semiconductor Manufacturing Ltd (corporation)

National University of Singapore

Harianto Wong

Lap Chan

Yang Pan

John Leonard Sudijono

Kin Leong Pey

Eng Hua Lim

Kong Hean Lee

Kin-Leong Pey

A method of fabrication of a metal lines without dishing using damascene and chemical-mechanical polish processes. A Key feature is the hard cap layer that is only formed over the trench opening. The hard cap layer prevents dishing of the metal line and also allows faster CMP than blanket polish stop layers. The method includes forming a first dielectric layer having a first trench opening over a semiconductor structure. A metal layer is deposited in the first trench opening. The metal layer has a dimple. The metal layer is preferably composed of Al or Cu. A hard mask is formed having a first opening over the first trench opening. The first opening is at least partially over first trench opening. A hard cap layer (e.g., W or WSi.sub.x) is selectively deposited on the metal layer exposed in the first opening. The hard cap layer, the hard mask, and the metal layer are chemical-mechanical polished to completely remove the hard mask resulting in a metal line having a 'dishing free' flat top surface. The chemical-mechanical polish rate of the hard cap is less than the rate of the metal layer.

Method to prevent dishing in damascene CMP process

A method is described for filling trenches in a substrate for shallow trench isolation or for a metal damascene structure which will prevent dishing when the substrate is planarized using chemical mechanical polishing. Trenches are formed in the substrate. A layer of first material is formed on the substrate, sidewalls of the trench, and bottom of the trench. A layer of second material is then formed on the layer of first material. The substrate is then planarized using a chemical mechanical polishing. The first material, second material, and parameters of the chemical mechanical polishing are chosen so that the removal rate of the first material is greater than the removal rate of the second material. The chemical mechanical polishing then results in a planar substrate with no dishing.

Method to prevent dishing in chemical mechanical polishing

An in-line non-destructive method is described for identifying phases in a micro-structure such as a fine line pattern. This is accomplished by observing the Raman spectrum of the micro-structure. A particular application is a silicide layer, prepared using the SALICIDE process, where the crystal phases before and after Rapid Thermal Anneal are often different. This is reflected by the appearance of different lines in the Raman spectra so that the fraction of each phase can be determined. If the silicide layer agglomerated during the anneal, this is also detected by the Raman spectrum. The method has been used successfully down to line widths of about 0.35 microns.

In-line process monitoring using micro-raman spectroscopy

A method for forming within a Field Effect Transistor (FET) for use within an integrated circuit a polycide gate electrode. There is first provided a semiconductor substrate. Formed upon the semiconductor is a patterned polysilicon layer. Formed then upon the semiconductor substrate and the patterned polysilicon layer is a blanket insulator layer. The blanket insulator layer is then patterned through planarizing to form a patterned planarized insulator layer while simultaneously exposing the surface of the patterned polysilicon layer. Finally, there is formed upon the exposed surface of the patterned polysilicon layer a patterned metal silicide layer. The patterned metal silicide layer and the patterned polysilicon layer form a polycide gate electrode. The metal silicide layer within the polycide gate electrode is not susceptible to encroachment upon adjoining insulator spacers or source/drain regions within the Field Effect Transistor (FET) within which is formed the polycide gate electrode.

Method for forming a polycide gate electrode

A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes. A second embodiment uses the self-aligned mask to form selectively a cobalt silicide on the polysilicon gate electrodes for low sheet resistance, while preventing the cobalt silicide from reacting with the adjacent titanium silicide source/drain regions.

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Singapore, Singapore

Harianto Wong