International Business Machines Corporation

Hari Krishnan Rajeev

Mary Prilotski Kusko

Steven Michael Douskey

Raghu Gaurav GopalaKrishnaSetty

James Douglas Warnock

Kenneth Pichamuthu

Baalaji Ramamoorthy Konda

Prakash Venkitaraman

Timothy C Taylor

Raghu G Gaurav

Todd L Cohen

Kanad Basu

Kelageri Nagaraj

Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

Operating pulsed latches on a variable power supply

According to an embodiment of the present invention, a computer-implemented method for testing a microelectronic chip is described. The method may include dividing, via a processor running a scanning engine, a plurality of sections of the microelectronic chip. Each of the plurality of sections includes at least two latch sets in at least one scan chain. The method may further include determining, via the processor, based on the dividing, whether each of the plurality of sections fail a data test. The determining comprises interleaving the plurality of sections by scanning, via the processor, an alternating latch set from each scan chain in a first section, and scanning an alternating latch set from each scan chain in a second section.

Bitwise rotating scan section for microelectronic chip testing and diagnostics

Embodiments include methods, and processing system, and computer program products providing portion isolation design to a chip design to facilitate partial-good portion isolation test of the chip. Aspects include: retrieving a chip design file of a chip, the chip design file having pin related information from a chip design database, generating, via a pin group utility module, a pin group file according to the pin related information retrieved, combining, via a portion wrapper insertion utility module, the pin group file with one or more portion netlists to form one or more localized portion wrapper segments, stitching, via the portion wrapper insertion utility module, the one or more localized portion wrapper segments to form a portion boundary wrapper chain, and inserting, via the portion wrapper insertion utility module, the portion boundary wrapper chain into the chip design file to facilitate partial-good portion isolation test.

Portion isolation architecture for chip isolation test

Crosstalk effects can be taken into account in automatic test pattern generation (ATPG) by providing crosstalk fault models, determining paths and/or nodes to be sensitized to activate each crosstalk fault, and optimizing to enable as many crosstalk faults as possible with a given pattern, subject to constraints. Constraints can include threshold numbers of endpoints/observation points and/or attempts to sensitize. Intermediate nodes in a crosstalk fault model path to an observation point can also be determined and/or sensitized.

Automatic test pattern generation (ATPG) considering crosstalk effects

A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.

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Kerala, India

Hari Krishnan Rajeev