Pure Storage, Inc.

Apple Inc.

Intel Corporation

Microsoft Technology Licensing, LLC

Hari Kannan

John Martin Hayes

Nenad Miladinovic

John D Davis

Zhangxi Tan

Robert H Lee

Boris Feigin

Yuhong Mao

Ying Gao

Peter E Kirkpatrick

Brian P Lilly

Gordon James Coleman

Pradeep Kanapathipillai

Mahnaz P Sadoughi-Yarandi

Brian Gold

Igor Ostrovsky

Gerard Richard Williams

Rajat Goel

Perumal R Subramoniam

Randy Zhao

Perumal R Subramonium

Ronald S Karr

Cary A Sandvig

Shantanu R Gupta

Jeffrey Vincent Tofano

Yijie Zhao

Fabio Margaglia

John Colgrove

Damian Pablo Yurzola

Emily Watkins

Vidyabhushan Mohan

Prashant Jain

Khurram Zaka Malik

Sankara Vaideeswaran

Melissa Kimble

Ravishankar Iyer

Andrew R Bernat

Stephan G Meier

Greg M Hess

Li Zhao

Donald K Newell

John H Mylius

Benjamin Scholbrock

Po-Yung Chang

Jaideep Moses

Ramesh Kumar Illikkal

Emily Potyraj

Mihai Budiu

Pavlos Konas

Svitlana Tumanova

John Roper

Matthew D Fleming

Russell Sears

Eric Mueller

Douglas Lother

Zhan Chen

Mark Heuchert

Ming-Ta Hsu

Caleb Gum

John Boyle

Eric Michael Verwillow

John Davis

Tan Zhangxi

A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.

Storage system with multiple write paths

A read request with a high priority indication is received. A determination as to whether an in progress flash programming operation would delay processing the read request for a threshold amount of time is made. In response to determining that the in progress flash programming operation delays processing the read request for the threshold amount of time, the in progress flash programming operation is interrupted.

Latency reduction of flash-based devices using programming interrupts

A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

Page write requirements for a distributed storage system

A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.

Dynamic migration techniques

In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.

Error correction incident tracking

A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

Background reads for solid state storage

A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.

Wear levelling for differing memory types

A method for a transactional commit in a storage unit is provided. The method includes receiving a logical record from a storage node into a transaction engine of a storage unit of the storage node and writing the logical record into a data structure of the transaction engine. The method includes writing, to a command queue of the transaction engine, an indication to perform an atomic update using the logical record and transferring each portion of the logical record from the data structure of the transaction engine to non-persistent memory of the storage unit as a committed transaction. A storage unit for a storage system is also provided.

Maintaining coherency in a distributed system

A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

Performing low latency operations using a distinct set of resources

Adjusting a variable parameter to increase reliability of stored data

A storage system is provided. The storage system include a primary storage node that includes a primary processing device. The primary storage node is communicatively coupled to a secondary storage node. The secondary storage node includes a secondary processing device and a set of non-volatile memory modules. The primary processing device is to identify one or more storage operations to be performed on the set of non-volatile memory modules of the secondary storage node and transmit one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device.

Device host operations in a storage system

A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.

Data rebuild based on solid state memory characteristics

A storage system with storage drives and a processing device establishes resiliency groups of storage system resources. The storage system determines an explicit trade-off between data survivability over resource failures and data capacity efficiency, for the resiliency groups. Responsive to adding at least one storage drive, the storage system establishes re-formed resiliency groups according to the explicit trade-off, without decreasing data survivability. The storage system may bias to have more and narrower resiliency groups to increase mean time to data loss.

Efficient partitioning for storage system resiliency groups

One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.

Resiliency management in a storage system

A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.

Dynamic buffer for storage system

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Sunnyvale, CA, United States of America

Hari Kannan