Apple Inc.

Hari Ganesh R Thirunageswaram

Peter F Holland

Mahesh B Chappalli

Brijesh Tripathi

Christopher P Tann

Malcolm D Gray

Jeffrey J Irwin

Kristan Jon Monsen

Eric Young

In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

General purpose input/output with hysteresis

The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).

Electronic display reduced blanking duration systems and methods

Devices and methods for underrun compensation are provided. By way of example, a technique for underrun compensation includes determining a particular one of a plurality of pixel configurations for a display. When an underrun condition is detected during processing of first image data via an image processing pipeline, at least a portion of requested image data for downstream processing has not yet been provided by an upstream processing component. Accordingly, upon detecting an underrun condition, underrun pixel data for the at least portion of the requested image data is generated, based upon the particular one of the plurality of pixel configurations.

Adjustable underrun outputs

Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. Each display pipeline generates dither noise for each frame in its entirety but only utilizes dither noise for the portion of the frame which is being driven to its respective portion of the display. This approach prevents visual artifacts from appearing at the dividing line between the first and second portions of the display.

Managing two dimensional structured noise when driving a display with multiple display pipes

A display pipe is configured to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame back to memory responsive to detecting static content in successive output frames. The display pipe may also be configured to determine to selectively allow write-back logic to operate when doing so will not cause a pixel underrun to the display. If an underrun might occur, write-back logic is temporarily disabled. If write-back is successful, the display pipe may read the compressed frame from memory for display instead of reading the source frames for compositing and display.

Managing back pressure during compressed frame writeback for idle screens

An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.

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Fremont, CA, United States of America

Hari Ganesh R Thirunageswaram