Stmicroelectronics Pvt. Ltd.

Hari Bilash Dubey

Sunil Chandra Kasanyal

Anshu Vij

Kapil Dixit

The present invention provides an output buffer providing multiple voltages including an arrangement of bootstrapping capacitors, and a charge replenishing mechanism which provides continuous pulses to the arrangement of bootstrapping capacitors, thereby, maintaining voltage on the bootstrapping capacitors.

Output buffer providing multiple voltages

A high performance adaptive load output buffer with fast switching of capacitive loads includes a first set of series connected complementary cascode structures having a first output node at the junction of the cascode connected p-channel device, a second output node at the junction of the two cascode structures, and a third output node at the junction of the cascode connected n-channel device. The buffer also may include at least one second set of series connected complementary cascode structures having the control terminal of the p-channel cascode structure of the second set connected to the inverted output from the first output node of first complementary cascode structure. The control terminal of the n-channel cascode structure of the second set may be connected to the inverted output from the third output node of first complementary cascode structure. The common terminal of the second cascode structure may be connected to the second output node of first complementary cascode structure and the output pad.

High performance adaptive load output buffer with fast switching of capacitive loads

A high speed voltage level translator having minimum power dissipation and reduced area, specifically in the sub 0.1 micron domain, includes a transistorized arrangement to receive a low voltage input signal and to control current in the translated high level voltage signal. The translator further provides a differential amplifier arrangement for receiving the low level voltage input signal and provides feedback signals to the transistorized arrangement thereby outputting a high level voltage translated signal.

High speed voltage level translator

The present invention provides a Differential Signaling line driver including a pre-emphasis circuit, which boosts the output drive current without any delay whenever there is a transition in the input signal to the driver, using the input signal itself to provide the pre-emphasis through a current steering circuit that switches the direction of drive currents to provide a differential output signal. A delayed signal is then used to disable the pre-emphasis after a short period.

Differential signaling driver

A CMOS to PECL voltage level converter includes a pad driver containing drive compensation circuitry and a feedback circuit for sensing the output drive level and providing control signals to the drive compensation circuitry for compensating for temperature and process variations while minimizing power consumption.

CMOS to PECL voltage level converter

A transceiver provides a high-speed transmission signal using shared resources and reduced area. A differential amplifier has its current source/sink connected to a supply terminal. A multiplexing circuit is configured to connect an input of the differential amplifier to an I/O pad so as to output a received input/output signal to internal integrated circuit logic during one mode, or alternatively connect an output of the differential amplifier to the I/O pad so as to output a signal received from the internal integrated circuit logic for input/output during another mode. A level translation operation on the signal may be performed with respect to outputting the signal received from the internal integrated circuit logic.

Transceiver providing high speed transmission signal using shared resources and reduced area

A Content Addressable Memory (CAM) cell is presented which provides for improved speed and enhanced reliability. The CAM architecture enables maximal conduction of one of the output series pass transistors in the case of a data mismatch during a search operation thereby producing a minimal voltage drop, low impedance path for charging the bootstrap capacitance at the enabled output controlled switch, and causes one of the series pass transistors to conduct for discharging the bootstrap capacitance at the beginning of the precharge period of the bit lines.

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DT-Ghazipur, India

Hari Bilash Dubey