Texas Instruments Corporation

Knights Technology, Inc.

Hari Balachandran

Jayashree Saxena

Pramodchandran Variyam

Jason Parker

Shawn Smith

Ken Butler

In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same frequency as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2 times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2 times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count. When the hit count and one of the predetermined set of threshold values are equivalent, the storage unit stores the value of N. A processing unit calculates the error of the PLL clock signal using each stored value of N which directly relates to the cumulative distribution of jitter found in the PLL clock signal.

All digital built-in self-test circuit for phase-locked loops

A system for generating a pruned diagnostic list of potential bridging faults in a circuit includes a pattern generator operable to generate test patterns for testing a circuit and a tester in communication with the pattern generator that is operable to apply the test patterns to the circuit and generate a plurality of resultant vectors. The system also includes a stuck-at fault dictionary including a list of a plurality of nets of the circuit, each net having at least one resultant vector that indicates a potential stuck-at fault at the net. The system further includes a test analysis tool in communication with the pattern generator and the tester, the test analysis tool operable to create an initial logical diagnostic list of tested nets of the circuit associated with the potential stuck-at faults indicated in the stuck-at fault dictionary, the initial logical diagnostic list created in response to the generated plurality of resultant vectors. The system also includes a diagnostic tool in communication with the test analysis tool and the tester, the diagnostic tool operable to create a final logical diagnostic list using the resultant vectors, stuck-at fault dictionary, and the initial logical diagnostic list, the final logical diagnostic list having a plurality of potential bridging faults ranked in order of logical probability.

System and method for pruning a bridging diagnostic list

An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps include creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, receiving the physical data associated with nets of the circuit, applying adjacency criteria to the physical data, generating a pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria, performing in-line inspection to obtain second localized probable defect data and correlating second localized portable defect data with the pruned diagnostic list.

System for mapping logical functional test data of logical integrated circuits to physical representation using pruned diagnostic list

The present invention, generally speaking, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the foregoing type to obtain X,Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout. In accordance with an exemplary embodiment, this mapping is performed by taking the output from a functional tester and translating it from a list of failed scan chains into a list of suspected netlist nodes. The X,Y coordinates of suspected netlist nodes are then identified and stored in a database, providing failure analysis and yield enhancement engineers a starting point for performing failure analysis and for immediately understanding whether &ldquo;in-line&rdquo; inspection data can account for a given failure. These nodes may then be crossmapped from the circuit design onto the chip's layout for each of multiple photomask layers within the design. Detailed failure data is gathered and stored at the wafer stage as part of a comprehensive program rather than on an as-needed basis at the packaged part stage. A voluminous amount of high-quality data is therefore obtained in an entirely automated fashion, as opposed to obtaining a comparatively minuscule amount of lesser-quality data in an exceedingly laborious fashion.

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Dallas, TX, United States of America

Hari Balachandran