Intel Corporation

Harel Frish

John Heck

Hari Mahalingam

Haisheng Rong

Kelly Christopher Magruder

Reece DeFrees

Seth M Slavin

Joshua Keener

Sansaptak W Dasgupta

Khaled Ahmed

Ansheng Liu

Pradeep Srinivasan

Mark Isenberger

Meer Nazmus Sakib

Wei Qian

Ganesh Balamurugan

Thomas L Sounart

Sergei L Sochava

Anup Pancholi

Ling Liao

Olufemi I Dosunmu

Israel Petronius

Aliasghar Eftekhar

Hao Li

Judson D Ryckman

Ranjeet Kumar

Duanni Huang

Saeed Fathololoumi

Lina He

George A Ghiurcan

Mengyuan Huang

Stefan Meister

Peicheng Liao

Chaoxuan Ma

Lingtao Liu

Wesley Harrison

Sungbong Park

Michael E Favaro

Nutan Gautam

Cung Tran

Shane Yerkes

Ron Friedman

Sean McCargar

Walter Garay

Stanley J Dobek

Eddie Bononcini

Eric Snow

Christopher Seibert

Jeremy Hicks

Randal Appleton

Carsten Brandt

Isako Hoshino

Kenneth Johnson

A method may include: forming a base layer on a substrate; forming a waveguide assembly on the base layer, where the waveguide assembly is surrounded by a cladding layer; forming a trench opening through the cladding layer and the base layer; forming an undercut void by etching the substrate through the trench opening, where the undercut void extends under the waveguide assembly and the base layer; and filling the trench opening with a filler to seal off the undercut void. Other embodiments are described and claimed.

Heating of thermo-optic device

Systems and methods for testing a photonic IC (PIC) with an optical probe having an out-of-plane edge coupler to convey test signals between the out-of-plane probe and an edge coupled photonic waveguide within a plane of the PIC. To accommodate dimensions of the optical probe, a test trench may be fabricated in the PIC near an edge coupler of the waveguide. The optical probe may be displaced along one or more axes relative to a prober to position a free end of the prober within the test trench and to align the probe's out-of-plane edge coupler with an edge coupler of a PIC waveguide. Accordingly, a PIC may be probed at the wafer-level, without first dicing a wafer into PIC chips or bars. The optical probe may be physically coupled to a prober through a contact sensor to detect and/or avoid physical contact between probe and PIC.

Contactless optical probing of edge-coupled photonic ICs

Silicon photonic integrated circuit (PIC) on a multi-zone semiconductor on insulator (SOI) substrate having at least a first zone and a second zone. Various optical devices of the PIC may be located above certain substrate zones that are most suitable. A first length of a photonic waveguide structure comprises the crystalline silicon and is within the first zone, while a second length of the waveguide structure is within the second zone. Within a first zone, the crystalline silicon layer is spaced apart from an underlying substrate material by a first thickness of dielectric material. Within the second zone, the crystalline silicon layer is spaced apart from the underlying substrate material by a second thickness of the dielectric material.

Silicon photonic integrated circuits on substrates with structured insulators having specific thicknesses in separate zones

Embodiments described herein may be related to apparatuses, processes, and techniques related to coherent optical receivers, including coherent receivers with integrated all-silicon waveguide photodetectors and tunable local oscillators implemented within CMOS technology. Embodiments are also directed to tunable silicon hybrid lasers with integrated temperature sensors to control wavelength. Embodiments are also directed to post-process phase correction of optical hybrid and nested I/Q modulators. Embodiments are also directed to demultiplexing photodetectors based on multiple microrings. In embodiments, all components may be implements on a silicon substrate. Other embodiments may be described and/or claimed.

Optical coherent receiver on a chip

Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

Embedded three-dimensional electrode capacitor

Embodiments of the present disclosure are directed to low numerical aperture (NA) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. In embodiments, the optical couplers may be positioned on a silicon substrate proximate to V-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. Other embodiments may be described and/or claimed.

Multi-layer silicon photonics apparatus

A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

III-N multichip modules and methods of fabrication

Embodiments may relate to a wavelength-division multiplexing (WDM) transceiver that has a silicon waveguide layer coupled with a silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may include a tapered portion that is coupled with the silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may be coupled with a first oxide layer with a first z-height, and the silicon nitride waveguide layer may be coupled with a second oxide layer with a second z-height that is greater than the first z-height. Other embodiments may be described or claimed.

Integrated photonic transceiver

Growing community of inventors

Albuquerque, NM, United States of America

Harel Frish