Samsung Electronics Co., Ltd.

Hareharan Nagarajan

Sajal Mittal

Abhishek Ghosh

Vinod Sharma

Aroma Bhat

Abdur Rakheeb

Rahul Kataria

Nandish Uppal Raravi

A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

Three-input exclusive NOR/OR gate using a CMOS circuit

Methods and apparatus for implementing a current-mirror based level shifter circuit are provided. The current-mirror based level shifter circuit includes a current-mirror circuit, a feedback control circuit, a power down circuit and a plurality of inverter circuits. The apparatus is configured to provide a wide voltage shifting range using the current-mirror based level shifter circuit. The apparatus comprising a feedback loop with two diode connected transistors may provide a constant drivability to the node that drives the output, when a current-mirror circuit is turned-off.

Current-mirror based level shifter circuit and methods for implementing the same

Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the Xand Xirrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.

Flip flop circuit

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Bengaluru, India

Hareharan Nagarajan