Qualcomm Incorporated

Northrop Grumman Systems Corporation

Wi-lan Inc.

Hardik M Patel

Todd Robert Sutton

Michael Lee McCloud

Frederic Bossu

Amit Mahajan

Francis M Ngai

Helena Deirdre O'Shea

Hua Guan

Prashanth Akula

Ali Taha

Frank B Winter

William R Goyette

Chris M Rosolowski

Eric Ian Mikuteit

Amy Derbyshire

Fan Yang

Hector Freires Corleto

Gregory Simon Walsh

Zoran Janosevic

David Coronel

James Stump

Laddan Hashemian

Eric C Johnston

Mathieu Jaloux

Eric Mikuteit

Hector Corleto

Certain aspects of the present disclosure provide a power supply system. The power supply system generally includes a first voltage regulator and a second voltage regulator, outputs of the first voltage regulator and the second voltage regulator being coupled to an output of the power supply system. The power supply system may also include a current balancer circuit configured to adjust an output current of the first voltage regulator based on determined headrooms of the first voltage regulator and the second voltage regulator.

Load balancing architecture for ganging voltage regulators

Exemplary embodiments are related to enhancing power efficiency of an electronic device. A device may include a power management module and a radio-frequency (RF) module coupled to the power management module. The device may further include a digital module coupled to each of the power management module and the RF module and configured to dynamically adjust at least one setting of the power management module based on one or more RF conditions.

Dynamic power management control

In one embodiment, a circuit comprises a sense circuit configured to sense an increase in an output voltage of a switching regulator under a light load condition. A pulse generating circuit generates a control signal to switch on and off a voltage input to the switching regulator. The pulse generating circuit reduces in a binary manner a switching frequency of the control signal under the light load condition as the sensed output voltage increases. As the output voltage rises, a clock signal is divided by two to remove every second pulse and applied to the pulse generating circuit. Further increases in the output voltage cause divisions of the clock frequency by four to remove 3 of 4 pulses so that only every fourth pulse remains. With output voltage increases, the frequency is divided by eight to remove 7 of 8 pulses so that every eighth pulse remains, and so forth.

Switch mode power supply including binary pulse skipping

A method and system for managing electrical current within a portable computing device ('PCD') includes assigning a priority to two or more communications supported by the PCD. A present level of a power supply for the PCD may be monitored by a communications power ('CP') manager module. Next, the CP manager module may determine if the two or more communications may be transmitted at the present level of the power supply. If the two or more communications cannot be transmitted at the present level of the power supply, then the CP manager module may determine if a timing of at least one of the communications may be adjusted. The CP manager module may also determine a theoretical power level adjustment for at least one of the communications. The two or more communications may be transmitted with any calculated timing off sets and power level adjustments.

Managing electrical current in a portable computing device when two or more communications overlap in drawing power during a transmission

Methods and apparatus for implementing a wireless communication transceiver having receive path performance diversity. The transceiver implements a plurality of signal paths that can be configured as diversity receive paths. Each of the plurality of signal paths includes a distinct RF filter. Each RF filter can be configured to provide a distinct jammer rejection profile. Each receive path also includes a jammer detector, that can be a multiple level jammer detector. Each jammer detector operates to control a level of processing gain applied to the signals in its receive path. The multiple gain scaled receive signals can be combined in a coherent combiner before being routed for further processing.

Transceiver with receive path performance diversity and combiner with jammer detect feedback

A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.

Multilayer passive circuit topology

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San Diego, CA, United States of America

Hardik M Patel