Apple Inc.

Hardik K Doshi

Joseph J Castro

Joshua P De Cesare

Timothy R Paaske

Michael J Smith

Jeffrey R Wilcox

Joel N Kerr

Kerry J Kopp

Xeno S Kovah

Corey T Kallenberg

Gopal Thirumalai Narayanan

Christopher J Noe

Nikolaj Schlej

Joshua H Berlin

Kevin H Alderfer

Michael W Murphy

Varaprasad V Lingutla

Craig S Forbell

Siddharth P Shah

Ezekiel T Runyon

Christopher M Aycock

Sreenivas Tallam

Andre M Glover

Deepak K Mishra

A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.

Systems and methods for PCI load balancing

One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.

Coordinated panic flow

A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.

Method and apparatus for secure system boot

A computing device may comprise a first processor and a secondary processor. The first processor may initiate a power management process transitioning the first processor from a first state to a second state and, upon reaching a predetermined step in the power management process, notify the secondary processor of the power management process. The secondary processor may initiate, in response to the notifying, a parallel power management process transitioning the secondary processor from an equivalent first state to an equivalent second state.

Booting and power management by coordinating operations between processors

A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

Control of power state transitions

A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.

Method and apparatus for boot variable protection

Booting and power management

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Los Altos, CA, United States of America

Hardik K Doshi