Synopsys, Inc.

Tokyo Electron Limited

Harbinder Singh

James Beausang

John Josef Hench

Sunil C Shah

Thorkell Gudmundsson

Ioannis Kanellakopoulos

Gurcan Aral

Denis Martin

Yaolong Tan

Amir Gholamhossein Zadeh Aghdam

Dhiraj Goswami

Robert L Walker

Ajay Khoche

Srinivas Ajjarapu

Amir Gholamhossein Zadeh Comordia Univ Aghdam

Cecilia Gabriela Galarza

Events that occur in a number of in domain communication channels where each channel is used by a communication service, are detected. A Bayesian Belief Network (BBN) defines a probabilistic cause-effect relationship between each cause and each effect on a victim channel. The probability of each of a number of possible causes as being a cause of interference in the victim channel is determined, by propagating observations of the interference backwards through the BBN.

Method and apparatus for impairment diagnosis in communication systems

A method and apparatus are disclosed. The method includes one or more of the following: compiling statistical models of physical layers of a communications system; creating a priori distributions of cross-talk transfer functions; storing the models and the a priori distribution in a storage medium; and using the models and the a priori distributions to diagnose probable causes of events detected in said communications system.

Design and architecture of an impairment diagnosis system for use in communications systems

A computer implemented process and system for electronic design automation (EDA) using groups of multiple cells having loop-back connections for modeling port electrical characteristics. Multi-bit cells have multiple gates of the same function implemented within a same cell. Multi-bit components have multiple multi-bit cells implemented within a same component. Scannable multi-bit cells and components are similar to multi-bit cells and components but contain scannable sequential elements with scan chains installed. Multi-bit cells may or may not have each sequential cells' input and each sequential cells' output available externally. The scannable sequential elements of a multi-bit component are ordered into a predefined scan chain which is defined by the library containing the multi-bit component or multi-bit cell. During scan replacement processes of the EDA compile process, multi-bit cells and components of the netlist are replaced with scannable multi-bit cells and components. Also, during optimization, multi-bit cells and components undergo equivalence replacement to meet specified constraints (e.g., area, performance, etc.). To model the electrical characteristics of the port during certain optimizations, loopback connections are applied to the multi-bit components from the scan out port to the scan in port of the multi-bit cell or component, therefore, one loopback connection spans multiple sequential cells within the multi-bit cell or component. During certain optimizations, loopback connections are applied to multiple sequential cells that are coupled together but do not necessarily reside in a multi-bit cell or component. By spanning multiple sequential cells, circuit degeneration is reduced thereby providing better circuit optimizations for netlists having scan circuitry.

Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics

A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.

Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker

A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality. The actual test point circuit may also be merged with other circuitries of the integrated circuit to produce a more efficient design.

Pre-synthesis test point insertion

A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device.sub.-- ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.

Instructions signature and primary input and primary output extraction

Method and system for performing automatic extraction and compliance

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San Jose, CA, United States of America

Harbinder Singh