Infineon Technologies Ag

Qimonda Ag

Harald Streif

Mike A Killian

Stefan Wuensche

Helmut Schneider

Oliver Kiehl

Ronny Schneider

Andre Sturm

The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.

Power savings for memory with error correction mode

A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a plurality of circuits is reduced so as to reduce gate induced leakage (GIDL) current associated with said plurality of circuits. During time intervals while in the standby mode, the voltage supplied to a subset of said plurality of circuits is increased to a level necessary for a refresh function associated with said subset of said plurality of circuits and then it is reduced upon completion of said refresh function. In the example a semiconductor memory device, the circuits that are manipulated in this manner are wordline driver circuits. A cyclical self-refresh operation is provided to refresh the WLs associated with subsets of the wordline driver circuits to reduce the overall GIDL current associated with the plurality of wordline driver circuits.

Gate induced drain leakage current reduction by voltage regulation of master wordline

A memory device () includes an array () of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder () is coupled to rows of memory cells while a column decoder () is coupled to columns of the memory cells. The column decoder () includes an enable input. A variable delay () has an output coupled to the enable input of the column decoder (). The variable delay () receives an indication (R/W') of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay () is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

Memory device with column select being variably delayed

A memory device () includes an array () of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder is coupled to rows of memory cells while a column decoder () is coupled to columns of the memory cells. The column decoder () includes an enable input. A variable delay () has an output coupled to the enable input of the column decoder (). The variable delay () receives an indication (R/W') of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay () is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch) and a filter (such as the filter). The latch tracks a reference signal at its input and reflects the reference signal at its output. The filter can be coupled to the output of the latch and may inject a delay to help eliminate the effects of glitches and noise. When the reference signal reaches a specified value, a control signal from the filter causes the latch to store the reference signal. A delay imparted by the filter ensures that the latch does not store the reference signal until a finite amount of time after the reference signal reaches the specified value.

Reference voltage detector for power-on sequence in a memory

Embodiments of the present invention generally provide a soft error-resistant latch circuit. The latch circuit generally includes first and second inverters, each formed by at least two transistors. At least one delay element decouples the gate of at least one of the transistors of one of the inverters from a diffusion area of at least one of the transistors of the other inverter.

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Burlington, VT, United States of America

Harald Streif