Infineon Technologies Ag

Qimonda Ag

Other

Harald Seidl

Martin Gutsche

Thomas Hecht

Bernhard Sell

Franz Kreupl

Stephan Kudelka

Martin Popp

Stefan Jakschik

Hans-Joachim Barth

Albert Birner

Ronald Kakoschke

Adolf Koller

Gunther Mackh

Bernd Goebel

Peter Moll

Uwe Schroeder

Dirk Schumann

Uwe Schröder

Jörn Lützen

Annette Sänger

Gerhard Leschik

Thomas Happ

Josef Willer

Helmut Horst Tews

Rajarao Jammy

Matthias Goldbach

Joseph Francis Shepard, Jr

Cay-Uwe Pinnow

Irene Lennox McStay

Alfred Kersch

Annette Saenger

Jean-Marc Rousseau

Annette S&auml;nger

Matthias Schmeide

Shrinivas Govindarajan

Uwe Paul Schr&ouml;der

Matthias Leonhardt

Werner Steinhögl

Manfred Hauf

The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Vertical interconnect structure, memory device and associated production method

The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is diced to produce a plurality of singulated chip stacks.

Method for producing chip stacks

A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.

Chip comprising a fill structure

The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is sawed to produce a plurality of singulated chip stacks.

Method for producing chip stacks, and associated chip stacks

One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope.

Memory device comprising select gate including carbon allotrope

The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory ('PCRAM'). In one disclosed method, a nanowire of non-conducting material is formed serving as a mould for producing a nanotube of conducting material. A volume of switching active material is deposited on top of the nanotube, so that the ring-shaped front face of the nanotube couples to the switching active material and thus forms a bottom electrode contact.

Phase change random access memory device with transistor, and method for fabricating a memory device

A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures.

Process for producing sublithographic structures

Method for producing a dielectric material on a semiconductor device and semiconductor device Method for producing a dielectric material on semiconductor device with an atomic layer deposition procedure, whereby an aluminum oxide nitride or a silicon oxide nitride or an aluminum silicon oxide nitride layer is deposited comprising a rare earth metal-element. The invention describes a semiconductor device with a dielectric layer comprising aluminum oxide nitride or silicon oxide nitride or an aluminum silicon oxide nitride comprising a rare earth metal element.

Method for producing a dielectric material on a semiconductor device and semiconductor device

One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.

Floating gate device with graphite floating gate

A memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory ('PCRAM'), with a transistor is disclosed. Further, the invention relates to a method for fabricating a memory device. According one embodiment of the invention, a memory device is provided, having at least one nanowire or nanotube or nanofibre access transistor. In one embodiment, the nanowire or nanotube or nanofibre access transistor directly contacts a switching active material of the memory device. According to an additional embodiment, a memory device includes at least one nanowire or nanotube or nanofibre transistor with a vertically arranged nanowire or nanotube or nanofibre.

Memory device, in particular phase change random access memory device with transistor, and method for fabricating a memory device

The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are mechanically stabilized.

Stacked capacitor array and fabrication method for a stacked capacitor array

Growing community of inventors

Poering, Germany

Harald Seidl