International Business Machines Corporation

International Buisiness Machines Corporatoin

Harald Folberth

Sourav Saha

Joachim Keinert

Harry S Barowski

Sven Peyer

Michael Kazda

Dilip Kumar

Hameedbasha Shaik

Sven Nitzsche

Paul Gerard Villarrubia

Erich Klink

Bernhard Korte

Stephan Held

Ajith Kumar M Chandrasekaran

Kurt Pollmann

Oliver Rettig

J&uuml;rgen Koehl

Jo Slashedrgen Koehl

Pietro Saccardi

To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Automated design closure with abutted hierarchy

Systems and methods to place latches during hierarchical integrated circuit development obtain an initial floor plan indicating a blocked region, two or more regions, and initial locations of components including the latches. A method includes identifying a subset of the latches that belong to a vector as a vector of latches, the subset of the latches being single-bit latches that must be placed in a same one of the two or more regions, and identifying a center of gravity (COG) of the vector of latches, the COG being a mean of geometric points corresponding with the subset of the latches. All of the subset of the latches are placed at the COG to generate an intermediate floor plan based on determining that the COG is not in the blocked region. A final design of the integrated circuit that is obtained based on the intermediate floor plan is provided for fabrication.

Placement of vectorized latches in hierarchical integrated circuit development

A method can include receiving design data of the integrated circuit, the design data indicates a set of sub-units partitioning an area of an integrated circuit, and a clock tree coupling the sub-units, the clock tree including a selected memory element, a predecessor memory element, and successor elements; determining a valid placement region for relocating the selected memory element; generating grid comprising first set of perpendicularly intersecting lines through the selected memory element, predecessor memory element, and successor elements; extending the grid to include second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines; determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and the successor elements; relocating the memory element to the determined point.

Constructing staging trees in hierarchical circuit designs

Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Layout of large block synthesis blocks in integrated circuits

A system and method place unit-level components in a macro within a unit of an integrated circuit that includes two or more of the units that each include two or more of the macros. The method includes detecting white space in a congestion plot of the macro. The white space represents potential placement areas for the unit-level components. The method also includes performing wire reach analysis between sources and sinks on different sides of the macro to determine an allowable region for the unit-level components, and deriving a buffer and latch placement reservation area in which to place the unit-level components based on the white space and the allowable region.

Placement clustering-based white space reservation

Respective large block synthesis (LBS) blocks of an integrated circuit (IC) are overlapped along a corner of each respective LBS block to form an overlap area having an area less than respective areas of respective LBS blocks that are overlapped. A first portion of the overlap area is allocated to a first LBS block and configured to be used by the first LBS block, and a second portion of the overlap area is allocated to a second LBS block and configured to be used by the second LBS block.

Area sharing between multiple large block synthesis (LBS) blocks

A method includes identifying a design area for a microelectronic device, where the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The method places a central latch in a center of the design area, where the central latch presents a connection point on a first level of the design area. Responsive to determining a sub-unit of the plurality of sub-units does not include a latch, the method creates a horizontal and vertical axis through the central latch, where the horizontal and vertical axis are bound by a perimeter of the design area. The method places a first set of latches for tiles created by the horizontal axis and the vertical axis on a second level of the design area, where each latch of the first set of latches is placed in a center of a single tile.

Clock control trees

A method, executed by a computer, for placing circuit elements includes determining an initial placement for a set of circuit elements corresponding to a circuit design, identifying a port for a circuit element of the set of circuit elements to provide an identified port, calculating a load-to-driver capacitance ratio for the identified port, determining an estimated operating parameter corresponding to the identified port if the load-to-driver capacitance ratio exceeds a selected threshold, and changing placement of the circuit element, or an associated driver, if the estimated operating parameter is outside an acceptable operating range. Changing placement of the circuit element or an associated driver can improve the estimated operating parameter corresponding to the identified port. In some embodiments, the estimated operating parameter is an estimated operating temperature.

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Boeblingen, Germany

Harald Folberth