Infineon Technologies Ag

Infineon Technologies LLC

Harald Bachhofer

Thomas Peter Haneder

Reinhard J Stengl

Hans Reisinger

Hermann Wendt

Wolfgang H&ouml;nlein

Volker Lehmann

Walter Hartner

Georg Braun

Martin Franosch

Wolfgang Hoenlein

Oswald Spindler

Gerrit Lange

Guenther Schindler

Rainer M Waser

Wolfgang Hönlein

Eugen Unger

Herbert Sch&auml;fer

Marc Ullmann

The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor

In a method for producing ferroelectric strontium bismuth tantalate having the composition Sr Bi Ta O (SBT) or Sr Bi (Ta, Nb) O (SBTN), the element strontium, which is normally present in an amount y&equals;2, is provided in excess in a range from 2.1&lE;y&lE;3.0. This makes it possible to carry out the heat treatment step for converting the deposited material into the ferroelectric phase at a temperature T , which is lower than 700&deg; C. In addition, the strontium content x can be reduced from a nominal value of 1 to 0.7.

Low-temperature processing of a ferroelectric strontium bismuth tantalate layer, and fabrication of ferroelectric components using the layer

A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor

In a ferroelectric transistor containing two source/drain zones with a channel region disposed there-between, a first dielectric intermediate layer containing Al O is disposed on a surface of the channel region. A ferroelectric layer and a gate electrode are disposed above the first dielectric intermediate layer. The utilization of Al O in the first dielectric intermediate layer results in the suppression of tunneling of compensation charges from the channel region into the first dielectric layer and thereby improves the time for data storage.

Ferroelectric transistor

A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.

Ferroelectric memory cell with diode structure to protect the ferroelectric during read operations

A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

Ferroelectric transistor and memory cell configuration with the ferroelectric transistor

A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Storage capacitor for a DRAM

A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

Capacitor for semiconductor configuration and method for fabricating a dielectric layer therefor

The crystallization temperature of a ferroelectric layer ( ) (dielectric) for a storage capacitor can be lowered by applying a very thin (CeO layer ( ) to a first platinum electrode layer ( ) of the storage capacitor before the ferroelectric layer is deposited. The dielectric layer ( ) deposited in amorphous state is then crystallized by a temperature treatment step at a temperature in the range between 590&deg; C. and 620&deg; C. A second electrode layer ( ) is then applied to complete the storage capacitor.

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Munich, Germany

Harald Bachhofer