Cypress Semiconductor Corporation

Monterey Research, LLC

Hapreet Sachar

Shenqing Fang

Kuo-Tung Chang

Hidehiko Shiraiwa

Chih-Yuh Yang

Youseok Suh

Meng Ding

Amol Ramesh Joshi

Tim Thurgate

David H Matsumoto

Lovejeet Singh

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

System and method for manufacturing self-aligned STI with single poly

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Milpitas, CA, United States of America

Hapreet Sachar