International Business Machines Corporation

Nvidia Corporation

Haoxing Ren

Ruchir Puri

Minsik Cho

Sourav Saha

Joachim Keinert

Hua Xiang

Harry S Barowski

Brucek Kurdo Khailany

Sridhar H Rangarajan

Charles Jay Alpert

Paul Gerard Villarrubia

Matthew Mantell Ziegler

Brian R Konigsburg

Jeonghee Shin

Indira Nair

Gi-Joon Nam

Victor N Kravets

Smita Krishnaswamy

Mary Prilotski Kusko

Tingdong Zhou

Walker Joseph Turner

Rangharajan Venkatesan

Ting Ku

Matthew Rudolph Fojtik

David John Geiger

George Ferenc Kokai

Sreedhar Pratty

Yanqing Zhang

Steve Haihang Dai

Muhammad Arif Mirza

Vidya Chhabria

Shaurakar Das

SeshasaiJyothi Kolli

Santosh Santosh

David James Hathaway

Hung Cai Ngo

Chin Ngai Sze

Bruce Martin Fleischer

Wiren Dale Becker

Shyam Ramji

Natarajan Viswanathan

Haifeng Qian

Alvan Wing Ng

Louise Helen Trevillyan

Eli Arbel

Xiaoping Tang

Karthikeyan Natarajan

Pinaki Chakrabarti

Jagannathan Narasimhan

Ronald Gene Walther

George Antony

David L Rude

Jeremy T Hopkins

Spencer K Millican

Rona Yaari

Zongyi Li

Dorothy Kucar

William R Migatz

Harbinder Sikka

Zhiyao Xie

Lijuan Luo

John Mack Isakson

Benjamin Andrew Keller

Paul Gerard Villarubia

Zahi M Kurzum

Yuzhe Ma

Nilesh A Modi

Sheng Ye

Haoyu Yang

Yi-Chen Lu

Tian Yang

The IR drop for a portion of a circuit may include a voltage drop across resistance, and may include a product of current I passing through resistance with a resistance value R. In order to determine IR drop for a circuit in a more accurate and efficient manner, a neural network produces coefficient maps (that each indicate a time-varying distribution of power within an associated portion of the circuit), and these coefficient maps are then used by the neural network to determine an IR drop for each of a plurality of portions of the circuit.

Determining IR drop

A VLSI placement optimization framework receives a cell connectivity representation and cell characteristics and uses self-supervised graph clustering to optimize cell cluster assignments for power, performance, and area (PPA). The framework provides cell clustering constraints as placement guidance to commercial placers. Specifically, graph learning techniques are used to formulate the PPA metrics as machine learning loss functions that can be minimized directly through gradient descent. The framework improves the PPA metrics at the placement stage and the improvements endure to the post-route stage.

VLSI placement optimization using self-supervised graph clustering

As integrated circuit geometries have shrunk, lithography simulation has developed to ensure that the masks used to fabricate the circuits satisfy the chip yield and fabrication turnaround time targets. To manufacture an integrated circuit (chip), an initial layout for the integrated circuit design is processed to compute a wafer image (e.g., resist material 'printed' on the wafer using photomasks). Lithography simulation processes the initial layout according to optical physics to compute an estimated wafer image without actually constructing the physical masks or consuming any wafer fabrication resources and may be used to confirm manufacturability of the design layout before it is fabricated. Performing lithography simulation using a dual-band neural network produces accurate results efficiently. Dual-band refers to a dual frequency band processing whereby the input layout (mask image) is separately processed by both a first and second branch to extract low-frequency (global) features and high-frequency (local) features, respectively.

Lithography simulation using a neural network

Today neural networks are used to enable autonomous vehicles and improve the quality of speech recognition, real-time language translation, and online search optimizations. However, operation of the neural networks for these applications consumes energy. Quantization of parameters used by the neural networks reduces the amount of memory needed to store the parameters while also reducing the power consumed during operation of the neural network. Matrix operations performed by the neural networks require many multiplication calculations, so reducing the number of bits that are multiplied reduces the energy that is consumed. Quantizing smaller sets of the parameters using a shared scale factor improves accuracy compared with quantizing larger sets of the parameters. Accuracy of the calculations may be maintained by quantizing and scaling the parameters using fine-grained per-vector scale factors. A vector includes one or more elements within a single dimension of a multi-dimensional matrix.

Fine-grained per-vector scaling for neural network quantization

To facilitate crosstalk analysis for an IC design, a plurality of input vectors are input into a gate-level simulation. In response, the gate-level simulation determines timing windows for all nets within the IC design, may perform aggressor pruning, and may then determine and output aggressor/victim pairs and associated features for the IC design. This gate-level simulation may be accelerated utilizing one or more graphics processor units (GPUs). Additionally, the aggressor/victim pairs and associated features for the IC design are then input into a trained machine learning environment, which outputs predicted delta delays for each of the aggressor/victim pairs. In this way, crosstalk analysis may be performed more accurately and efficiently.

Reducing crosstalk pessimism using GPU-accelerated gate simulation and machine learning

To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

Rail power density aware standard cell placement for integrated circuits

A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

Layout parasitics and device parameter prediction using graph neural networks

A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.

Standard cell layout generation with applied artificial intelligence

The disclosure provides a general solution for determining connections between terminals of various types of circuits using machine learning (ML). A ML method that uses reinforcement learning (RL), such as deep RL, to determine and optimize routing of circuit connections using a game process is provided. In one example a method of determining routing connection includes: (1) receiving a circuit design having known terminal groups, (2) establishing terminal positions for the terminal groups in a routing environment, and (3) determining, by the RL agent, routes of nets between the known terminal groups employing a model that is independent of a number of the nets of the circuit. A method of creating a model for routing nets using RL, a method of employing a game for training a RL agent to determine routing connections, and a RL agent for routing connections of a circuit are also disclosed.

Routing connections in integrated circuits based on reinforcement learning

IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

IR drop prediction with maximum convolutional neural network

A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Integrated circuit design changes using through-silicon vias

Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Deep learning testability analysis with graph convolutional networks

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Austin, TX, United States of America

Haoxing Ren