University of Florida Research Foundation Inc

Haoting Shen

Mark M Tehranipoor

Domenic J Forte

Navid Asadizanjani

Kun Yang

Swarup Bhunia

Damon Woodard

Huanyu Wang

Nidish Vashistha

Bicky Shakya

Mir Tanjidur Rahman

Qihang Shi

Ulbert Botero

A pyramid structure to mitigate optical probing attacks in ICs by scrambling the measurements reflected by a laser pulse is disclosed. The pyramid structure is applied to selected areas at the bottom surface of the metal traces in metal layer to circumvent the extra silicon layer and thus minimize the changes to the conventional device structures. The pyramid structure includes randomized pyramids at nanometer scale. Optical simulation results show the pyramidized metal surface is able to prevent optical probing attacks. The fabrication of pyramids is CMOS compatible as well. Optical simulations are performed to analyze the impact these nano-scaled pyramids in a laser voltage probing attacking model. The nanopyramid can disturb the optical measurements enough to make the attacks practically infeasible. In addition, the nanopyramid structure countermeasure works in a passive mode without consuming any energy.

Optical scrambler with nano-pyramids

Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.

Prevention of front-side probing attacks

Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. The cell camouflaging covert gate leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. A comprehensive security analysis of the covert gate shows that it achieves high resiliency against SAT and test-based attacks at very low overheads. Models are derived to characterize the covert cells, and metrics are developed to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Covert gates to protect gate-level semiconductors

A method of detecting hardware Trojans in an IC includes providing a golden IC layout data set or SEM image data taken at long dwelling time on an active area of the golden IC after polishing it from the backside. Next, the IC under authentication (IUA) sample is prepared for fast SEM imagining (shorter dwelling time) after backside thinning. Next step is to perform image processing on the IUA's SEM image, which includes histogram equalization with noise filtering using Gaussian and Median filters. In the last step, the IUA sample data with the shorter dwelling time is compared with the golden IC layout data or the golden image data from high quality (longer dwelling time) SEM scanning process. At the end the result of the comparison is used to identify hardware Trojans.

Hardware trojan scanner

An unclonable chipless radio frequency identification (RFID) tag and corresponding cross-registration methods of determining an identity and/or tag signature of an RFID tag are described. In an example embodiment, an unclonable chipless RFID tag comprises a first tag portion comprising one or more first conductive members unremovably secured to a dielectric item; and a second tag portion comprising packaging conductive pattern. The first tag portion and the second tag portion are in a static or fixed physical relationship with respect to one another.

Cross-registration for unclonable chipless RFID tags

A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.

Vanishing via for hardware IP protection from reverse engineering

Chipless RFID tags and methods of using the same are provided. Each RFID tag provided herein can generate a unique and unclonable (unclonable chipless RFID, or UCR) identifier from its intrinsically random manufacturing process. The UCR device can monitor increase in storage temperature beyond that which is appropriate for a specific commodity to which the device is attached.

Growing community of inventors

Tallahassee, FL, United States of America

Haoting Shen