Fujitsu Semiconductor Limited

Intel Corporation

Haolu Xie

Patrick Rakers

Manish N Shah

Chuanzhao Yu

Chi-Taou Robert Tsai

Dave Newman

A shield for differential transmission lines formed in a first metal layer may include one or more floating shields, each floating shield comprising an upper-side tile formed in a second metal layer of the integrated circuit adjacent to the first metal layer, a lower-side tile formed in a third metal layer of the integrated circuit adjacent to the first metal layer and non-adjacent to the second metal layer, and at least one via configured to electrically couple the upper-side tile at an end of the length of the upper-side tile to the lower-side tile and at an end of the length of the lower-side tile.

Differential transmission line shielded by two or more spaced groups of shields

A mixer may include a linearization circuit. The linearization circuit may include and operation amplifier, a first pass device, a second pass device, a first feedback resistor, and a second feedback resistor. Each of the first pass device and the second pass device may have a gate terminal, a first non-gate terminal, and a second non-gate terminal and coupled to its gate terminal to an output terminal of the operational amplifier and configured to be coupled at its first non-gate terminal to a high potential source. Each of the first feedback resistor and the second feedback resistor may have a first terminal and a second terminal, the first terminal coupled to the positive input terminal of the operational amplifier and the second terminal coupled to the second non-gate terminal of an associated pass device and the positive polarity of the differential baseband output.

System and method for linearization of a mixer

A frequency divider with a twenty-five percent duty cycle is disclosed. A frequency divider may include an input configured to receive a clock signal, each cycle of the clock signal including a first phase and a second phase, a plurality of latches, and a plurality of three-state circuits wherein a first of the plurality of three-state circuits is configured to drive a first twenty-five percent duty cycle signal from within the first three-state circuit high during a first phase of a first of two clock cycles.

Technique to generate divide by two and 25% duty cycle

A technique for improving the linearity of a mixer is disclosed. A converter may include a mixer comprising a first metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a first conducting terminal coupled to an input of the converter, and a second conducting terminal coupled to an output of the converter, and a mixer driver having a first output coupled to the gate of the first MOSFET, the mixer driver configured to receive a local-oscillator signal having a first phase and a second phase, drive the first MOSFET off during the first phase of the local-oscillator signal, drive the first MOSFET on for a first period of time in response to a transition from the first phase of the local-oscillator signal to the second phase of the local-oscillator signal, and force the gate of the first MOSFET into a high impedance state for a second period of time during the second phase of the local-oscillator signal and after the expiration of the first period of time.

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Chandler, AZ, United States of America

Haolu Xie