Credo Technology Group Limited

Marvell International Limited

Credo Semiconductor (hong Kong) Limited

Haoli Qian

Junqing Phil Sun

Runsheng He

Fang Cai

William Lo

Hui Wang

Yifei Dai

Ping Zheng

Junqing (Phil) Sun

Yi-Chun Chen

Jeffrey Choun

Jamal Riani

Chee Hoe Chu

Xing Wu

Zhipei Chi

Xiang Guang Feng

Donald Barnetson

Tianchen Luo

Calvin Xiong Fang

Ashwin Upadhya

Sheng Huang

Jeff Twombly

Yu Liao

Xiang Gao

Yat-Tung Lam

Arshan Aga

Lawrence Chi Fung Cheng

William J Brennan

Baohua Chen

Hung-Yi Chen

Haihui Luo

James Bartenslager

Jeffrey Twombly

Chee Hoa Chu

Ruiqing Sun

Evan Lin

In-band communication methods and transceivers are provided to enable protocol-agnostic management channel. One illustrative in-band communications method includes: buffering an outbound data stream from a host-side receiver with a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing the outbound data stream with an additional word after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and idle words with adjacent message words potentially separated by a predetermined number of idle words.

SerDes method and device having a protocol-agnostic in-band management channel

Integrated circuit transceivers having digital timing recovery loops with phase interpolation may incorporate dynamic loop gains to compensate for nonlinearities of the phase interpolation. An illustrative receiver circuit includes: a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal. The timing error estimator produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

Dynamic timing loop gain to compensate phase interpolation nonlinearities

Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.

Transitioning between signal constellations

Cable designs and methods are provided herein to enable remote end access to active cable controllers for monitoring and upgrade operations. One illustrative network cable design includes: a first end connector configured to couple with a first host port and a second end connector configured to couple with a second host port, each of the first and second end connectors configured to convey a data stream in each direction via optical or electrical conductors connected between the first and second end connectors; a controller and a powered transceiver circuit included in the first end connector, the controller operable to configure operation of the powered transceiver circuit; and electrical contacts in the second end connector for a management bus to convey information from the second host port to the controller in the first end connector.

Active cable with remote end control access

Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.

Ethernet link extension method and device

Active cables and communication methods can provide data path redundancy with power sharing. In one illustrative cable implementation, the cable includes a first connector with contacts to supply power to circuitry in the first connector; a second connector with contacts to supply power to a component of the circuitry in the first connector via a first connection that prevents reverse current flow; and a third connector with contacts to supply power to the same component via a second connection that prevents reverse current flow. An illustrative method implementation includes: using contacts of a first connector to supply power to circuitry in the first connector; and using contacts in each of multiple redundant connectors to supply power to a component of said circuitry in the first connector via a corresponding diodic or switched connection that prevents reverse current flow.

Active redundant Y-cable with power sharing

Receivers and receiving methods having maximum likelihood sequence detection with pseudo partial response equalization. One illustrative receiver includes: a feedforward equalizer that produces an equalized receive signal by diminishing a receive signal's intersymbol interference; a decision element that derives initial symbol decisions from samples of the equalized receive signal; and a filter that applies a partial response to the equalized receive signal or to an equalization error signal to produce input for a maximum likelihood sequence detector (MLSD). The MLSD may be a reduced complexity detector that derives a final sequence of symbol decisions by evaluating state metrics only for each initial symbol decision and its competing symbol decision.

Receiver using pseudo partial response maximum likelihood sequence detection

Active Ethernet cables that provide data path redundancy. One illustrative cable embodiment includes a first connector connected to each of a second and third connectors, the first connector including a multiplexer that couples a data stream from a selectable one of the second and third connectors to an output of the first connector. One illustrative method embodiment includes: producing from an output of a first connector a data stream from a currently selected one of multiple redundant connectors; monitoring the data stream for a fault associated with the currently selected one of multiple redundant connectors; and responsive to detecting said fault, producing from the output of the first connector a data stream from a different selected one of the multiple redundant connectors.

Active ethernet cable with broadcasting and multiplexing for data path redundancy

Transmit-side equalization is disclosed for network devices and network communications methods employing onboard/co-packaged optics. An illustrative network device includes a substrate having a host device IC (integrated circuit) and an optical module IC connected by a short-reach link. The optical module IC having a transmit chain includes a CTLE (continuous time linear equalizer) to at least partly compensate for a channel response of the short-reach link, and a driver that amplifies an output of the CTLE for a photoemitter that couples to an optical fiber. The host device IC includes: a parallel-to-serial converter that produces a digital symbol stream; a digital to analog converter that supplies an analog signal to the short-reach link; and a pre-equalizer coupling the parallel-to-serial converter to the digital-to-analog converter, the pre-equalizer filtering the digital symbol stream to at least partly compensate for a channel response of a combined channel that includes the short-reach link, the CTLE, the driver, and the photoemitter.

Onboard/co-packaged optics with transmit-side equalization

Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.

Equalizer with perturbation effect based adaptation

An illustrative spread spectrum clocking (SSC) converter includes: a deserializer to receive a data stream with an unmodulated clock; a memory coupled to the deserializer to buffer the data stream; and a serializer coupled to the memory to retransmit the data stream with a spread spectrum clock. One illustrative conversion method, which may be implemented on a monolithic integrated circuit device, includes: receiving a data stream from an external transmitter in an unmodulated clock domain; storing the data stream in a buffer; and retransmitting the data stream with a spread spectrum clock. Such converters and methods may be employed in an illustrative system having: a test module to generate test data streams and to analyze result data streams for verifying operation of one or more devices under test in a spread spectrum clock domain as the test module operates in an unmodulated clock domain.

Spread spectrum clock converter

Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed.

Retimer training during link speed negotiation and link training

An illustrative digital communications method includes: filtering a receive signal to provide a filtered receive signal; deriving symbol decisions from the filtered receive signal; detecting a baud rate of the receive signal; adapting one or more coefficients of the filter if the baud rate is above a predetermined rate; and inhibiting coefficient adaptation if the baud rate is below the predetermined rate. The method may be implemented in a receiver having: a filter to convert a receive signal into a filtered receive signal; a decision element coupled to the filter to derive symbol decisions; a baud rate detector to detect a baud rate of the receive signal; and an adaptation module to adapt one or more coefficients of the filter if the baud rate is above a predetermined rate, the baud rate detector inhibiting adaptation if the baud rate is below the predetermined rate.

Equalizer training during link speed negotiation

Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder ('CSA') tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation. In an illustrative receiver, the filter is coupled to a decision element that derives a sequence of symbol decisions.

Digital filtering using combined approximate summation of partial products

An illustrative embodiment of a disclosed physical layer interface device includes: a first transmitter and a first receiver for a primary data path; a second transmitter and a second receiver for a secondary data path; a third transmitter and a third receiver for a non-redundant data path; and a multiplexer. The third receiver is coupled to provide a data stream received from the non-redundant data path concurrently to the first and second transmitters, and the multiplexer provides the third transmitter with a selected one of the data stream received via the primary data path and the data stream received via the secondary data path. Disclosed network switch embodiments employ the illustrative physical layer interface to provide internal or external data path redundancy for traffic handled by the network switch.

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Fremont, CA, United States of America

Haoli Qian