Skhynix Inc.

Haobo Wang

Fan Zhang

Meysam Asadi

Aman Bhatia

Xuanxuan Lu

Chenrong Xiong

Hongwei Duan

Jaeyoung Jang

Qiuju Diao

Seyhan Karakulak

Hui-Chun Wu

Jiangnan Xia

Devices, systems, and methods for improving performance of a memory device are described. An example method includes extracting parameters, which include a read threshold set, from each of a first set of host reads, replacing, based on the parameters, at least one host read from a second set of host reads by at least one host read from the first set of host reads, using a deep neural network (DNN) to generate an updated read threshold set, wherein an input to the DNN comprises the parameters from each of the second set of host reads subsequent to the replacing, and applying the updated read threshold set to the memory device to retrieve information from the memory device. In an example, the number of the first set of host reads is at least two orders of magnitude greater than the number of the second set of host reads.

Tracking read voltages in memory devices using deep neural networks

A scheme for encoding and decoding a codeword into which address information is embedded. A write operation for this scheme includes generating tagging information including address information; encoding user information, meta information, the tagging information and additional shortened bits to generate parity information; generating a codeword including the user information, the meta information and the parity information; and storing the codeword in a memory device.

Address embedding for encoder and decoder and data processing method thereof

Techniques for adjusting log likelihood ratios in a decoder may include determining an assist read (AR) zone based on performing assist reads (AR) of multibit memory cells of a memory. Soft reads of the multibit memory cells may be performed to determine a bin within the AR zone for each bit of the data stored in the memory cells. Each bin is associated with a log likelihood ratio (LLR) value. Error correction decoding on the data stored in the memory cells may be performed followed by collecting statistics on the decoded data for each bin in each AR zone. A hard error percentage may be computed for each AR zone based on the collected statistics, and one or more LLR values may be adjusted based on the hard error percentage.

Log likelihood ratios adjustment based on error tracker

Decoding method and memory system which group bits in irregular LDPC codes having similar degrees of convergence into respective degree groups, classify the degree groups according to a metric indicative of a number of decoding iterations for convergence, divide a time period for convergence of the decoding iterations into different zones for the processing of selected degree groups within each zone, and skip decoding of the bits in a non-converging zone where the bits are not converging.

Method and system for fast column processing for highly irregular LDPC codes

A memory system or a method for estimating channel information to be used for error decoding. The memory system or the method a) performs one or more read operations on a page selected from among the plurality of pages using a target read threshold, b) obtains the target read threshold, a historical read threshold voltage set associated with failed read operations of the selected page, checksum values, and asymmetric ratios of ones count and zeros count which are associated with the historical read threshold voltage set, c) provides the obtained target read threshold, historical read threshold voltage set, checksum values and asymmetric ratios as input information to a neural network, and d) predicts, by the neural network, channel information at the target read threshold based on the input information and a set activation function.

System and method for history-based non-parametric channel information prediciton using a deep neural network

Decoding method and memory system that classify check nodes in a matrix having irregular check node weights into different groups according to the check node weights, apply different scaling factors to respective constant node to variable node (C2V) messages in the different groups of the check nodes, and optionally add a compensation term to at least one of the C2V messages of the MS decoder.

Min-sum decoder for row-irregular low density parity check codes

Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

Out-of-order bit-flipping decoders for non-volatile memory devices

To improve error correction when errors occur in consecutive bits of user data, the user data can be stored in an interleaved manner. Data of a data unit can be interleaved to generate a permutated data unit. A checksum of the permutated data unit can then be calculated, and an error correction code can be generated over the data unit and the checksum. The error correction code can also be interleaved to generate a permutated error correction code. The permutated data unit, the checksum, and the permutated error correction code can then be concatenated to generate a storage data unit for storage in a memory.

Data interleaver for burst error correction

A method for operating an MS decoder and an associated memory system utilizing the MS decoder. The method determines an operation mode of the MS decoder. For each variable node, the method calculates a variable to check node VC message. The method stores, in a check node unit CNU memory, check information associated with the calculated VC message according to the operation mode. The check information includes full information when the operation mode is a high precision mode, and partial information when the operation mode is a low precision mode.

Hybrid precision MS decoder to reduce gate-count for long codes

A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.

Bit-flipping decoder and decoding method for irregular codes

A controller estimates optimal read threshold values for a memory device using deep learning. The memory device includes multiple pages coupled to select word lines in a memory region. The controller performs multiple read operations on a select type of page for each word line using multiple read threshold sets, obtains fail bit count (FBC) information associated with each read operation, and determines an optimal read threshold set for each word line based on the FBC information. When optimal read threshold sets for the select word lines are different each other, the controller predicts a best read threshold set using the optimal read threshold sets.

Read threshold estimation systems and methods using deep learning

An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.

Parallel system to calculate low density parity check

A controller optimizes read threshold values for a memory device using domain transformation. The controller determines, for decoded data of each read operation, an asymmetric ratio (AR) and a number of unsatisfied checks (USCs), the AR indicating a ratio of a number of a first binary value to a number of a second binary value in the decoded data. The controller determines a Z-axis such that AR values of threshold sets are arranged in a set order along the Z-axis. The controller determines an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value.

Read threshold optimization systems and methods using domain transformation

Decoding method and memory system that decodes data and estimates a weighted checksum on the decoded data to determine whether the decoding is successful. The weighted checksum is calculated based on a first group and a second group, the first group is associated with weights for high degree nodes of an irregular parity check matrix, and the second group is associated with weights for low degree nodes of the irregular parity check matrix.

On-the-fly scaling factor change for irregular LDPC codes

A scheme for non-parametric optimal read threshold estimation of a memory system. The memory system includes a memory device including pages and a controller including a neural network. The controller performs read operations on a selected page using a read threshold set; obtain the read threshold set, a checksum value and an asymmetric ratio of ones count and zeros count which are associated with decoding of the selected page according to each of the read operations; provide the obtained read threshold set, the checksum value and the asymmetric ratio as input information to the neural network; and estimate, by the neural network, an optimal read threshold voltage based on the input information and weights including a combination of multiple matrices and bias vectors.

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Haobo Wang